On Wed, 3 Jun 2020 at 02:14, Richard Henderson <richard.hender...@linaro.org> wrote: > > We now implement all of the components of MTE, without actually > supporting any tagged memory. All MTE instructions will work, > trivially, so we can enable support. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > v6: Delay user-only cpu reset bits to the user-only patch set. > --- > target/arm/cpu64.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index cbc5c3868f..e4bce55c5f 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -655,6 +655,7 @@ static void aarch64_max_initfn(Object *obj) > > t = cpu->isar.id_aa64pfr1; > t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); > + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); > cpu->isar.id_aa64pfr1 = t;
If we don't actually have tagged memory yet should we really set the MTE field to 2 rather than 1 ? thanks -- PMM
