On Fri, Jun 5, 2020 at 12:42 AM Bin Meng <bmeng...@gmail.com> wrote:
>
> From: Bin Meng <bin.m...@windriver.com>
>
> There is no need to have two functions that have almost the same
> codes for 32-bit and 64-bit gcsu CPUs.
>
> Signed-off-by: Bin Meng <bin.m...@windriver.com>
> ---
>
> target/riscv/cpu.c | 20 ++++++--------------
> 1 file changed, 6 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d38d829..e66488f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -134,16 +134,16 @@ static void riscv_base_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> +static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
Could we change the function names to rvxx_*?
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> +#if defined(TARGET_RISCV32)
> +
> static void rv32imcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
>
> #elif defined(TARGET_RISCV64)
>
> -static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> -}
> -
> static void rv64imacu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -597,11 +589,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,
> rv32gcsu_priv1_10_0_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,
> rvnn_gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,
> rv64gcsu_priv1_10_0_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,
> rvnn_gcsu_priv1_10_0_cpu_init),
> #endif
> };
>
> --
> 2.7.4
>
>
