Hi Ramon, > -----Original Message----- > From: Ramon Fried <rfried....@gmail.com> > Sent: Monday, May 4, 2020 9:20 PM > To: Sai Pavan Boddu <saip...@xilinx.com> > Cc: Edgar E. Iglesias <edgar.igles...@gmail.com>; Alistair Francis > <alistair.fran...@wdc.com>; Peter Maydell <peter.mayd...@linaro.org>; > Jason Wang <jasow...@redhat.com>; Markus Armbruster > <arm...@redhat.com>; Philippe Mathieu-Daudé <phi...@redhat.com>; > Tong Ho <to...@xilinx.com>; open list:Xilinx Zynq <qemu- > a...@nongnu.org>; QEMU Developers <qemu-devel@nongnu.org> > Subject: Re: [PATCH v2 00/10] Cadence GEM Fixes > > On Mon, May 4, 2020 at 5:14 PM Sai Pavan Boddu > <sai.pavan.bo...@xilinx.com> wrote: > > > > Hi, > > > > Following patch series fixes issues with priority queues, Adds JUMBO > > Frame support, Makes Debug statements compilable & Fixes related to > > multicast frames. > > > > Changes for V2: > > Fixed build failure on fedora docker machine > > Fix buggy debug print to use sized integer casting > > > > Sai Pavan Boddu (9): > > net: cadence_gem: Fix debug statements > > net: cadence_gem: Fix the queue address update during wrap around > > net: cadence_gem: Fix irq update w.r.t queue > > net: cadence_gem: Define access permission for interrupt registers > > net: cadence_gem: Set ISR according to queue in use > > net: cadence_gem: Add support for jumbo frames > > net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg > > net: cadence_gem: Update the reset value for interrupt mask register > > net: cadence_gem: TX_LAST bit should be set by guest > > > > Tong Ho (1): > > net: cadence_gem: Fix RX address filtering > > > > hw/net/cadence_gem.c | 167 > > +++++++++++++++++++++++++++++---------------------- > > 1 file changed, 94 insertions(+), 73 deletions(-) > > > > -- > > 2.7.4 > > > Hey. did you test these with 64 descriptor addressing ? [Sai Pavan Boddu] Tested it with a BareMetal application.
> I can test it for you if you need. [Sai Pavan Boddu] Yes, would be nice, if you can review. Thanks, Sai Pavan > Thanks, > Ramon.
