On Mar 31 01:55, Keith Busch wrote: > On Mon, Mar 30, 2020 at 09:46:56AM -0700, Andrzej Jakowski wrote: > > This patch introduces support for PMR that has been defined as part of NVMe > > 1.4 > > spec. User can now specify a pmrdev option that should point to > > HostMemoryBackend. > > pmrdev memory region will subsequently be exposed as PCI BAR 2 in emulated > > NVMe > > device. Guest OS can perform mmio read and writes to the PMR region that > > will stay > > persistent across system reboot. > > Looks pretty good to me. > > Reviewed-by: Keith Busch <kbu...@kernel.org> > > For a possible future extention, it could be interesting to select the > BAR for PMR dynamically, so that you could have CMB and PMR enabled on > the same device. >
I thought about the same thing, but this would require disabling MSI-X right? Otherwise there is not enough room. AFAIU, the iomem takes up BAR0 and BAR1, CMB (or PMR) uses BAR2 and BAR3 and MSI-X uses BAR4 or 5.
