On 3/17/20 8:06 AM, LIU Zhiwei wrote: > Vector AMOs operate as if aq and rl bits were zero on each element > with regard to ordering relative to other instructions in the same hart. > Vector AMOs provide no ordering guarantee between element operations > in the same vector AMO instruction > > Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com> > --- > target/riscv/helper.h | 29 +++++ > target/riscv/insn32-64.decode | 11 ++ > target/riscv/insn32.decode | 13 +++ > target/riscv/insn_trans/trans_rvv.inc.c | 134 ++++++++++++++++++++++ > target/riscv/internals.h | 1 + > target/riscv/vector_helper.c | 143 ++++++++++++++++++++++++ > 6 files changed, 331 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
