On Fri, 6 Mar 2020, Mark Cave-Ayland wrote:
On 05/03/2020 23:35, BALATON Zoltan wrote:
On real hardware this may be true but in QEMU how would it otherwise raise the
correct interrupt line the guest expects? This probably does not matter for
pegasos2
but I think is needed for 100% native mode used with the fulong2e so it gets
the IRQ
it expects.
That's easy - remember that both the PCI and IRQ interrupts are separate pins
on the
chip, so all that needs to be done is expose the legacy IRQ via qdev and use
that to
wire it up to your interrupt controller.
This "chip" is part of an integrated southbridge/superio/everything chip
the also includes the two PICs and how they are internally connected is
not known so we would be guessing here anyway. I don't see a need to make
it more complicated than it is now by modeling internal pins but how would
I wire up gpio to the i8259 model and where should I connect the PCI irq?
Okay so this is interesting: I've been switching between the VT8231 and the
VT82C686B
datasheets, and there is a difference here. You are correct in what you say
above in
that the 8231 docs specify that this is set to 1, but on the 686B this is
clearly not
the case.
The 82C686B says this reg can be 0 or 1, where 0 is legacy interrupt
routing and 1 is native mode. Given that we only model native mode of the
chip it does not make sense to set it to anything else than 1 and setting
it to 0 confuses MorphOS and Linux on pegasos2 while setting it to 1 works
with everything I've tried both on pegasos2 and fulong2e even if that may
not completely match how it's implemented in hardware.
What is rather unusual here is that both the 8231 and 686B have exactly the same
device and vendor ids, so I'm not sure how you'd distinguish between them?
Guests distinguish by looking at the parent device (function 0) which is
the chip this IDE device is part of (on function 1).
Regards,
BALATON Zoltan
