This is not related to the patch but there is one other corner issue with the load and clear instructions.
When the target register is GR0, the instruction may be implemented as a normal load and clear which clears memory, or it may be aliased to the equivalent-sized load instruction, in which case it behaves exactly like that prefetch instruction and does not clear the data in memory. See page 6-12 on PA 2.0 architecture. Don't know what was actually done. Regards, Dave -- John David Anglin dave.ang...@bell.net
