On 11/15/19 6:30 PM, Alex Bennée wrote:
> +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
> +{
> + ARMCPU *cpu = ARM_CPU(cs);
> + GString *s = g_string_new(NULL);
> + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
> + g_autoptr(GString) ts = g_string_new("");
> + g_autoptr(GString) us = g_string_new("");
> + int i, j;
> + info->num = 0;
> + g_string_printf(s, "<?xml version=\"1.0\"?>");
> + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
> + g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");
> + /* first define types and the union they belong to */
> + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
> + int count = 128 / vec_lanes[i].size;
> + g_string_printf(ts, "vq%d%s", count, vec_lanes[i].suffix);
> + g_string_append_printf(s, "<vector id=\"%s\" type=\"%s\"
> count=\"%d\"/>",
> + ts->str, vec_lanes[i].gdb_type, count);
> + g_string_append_printf(us, "<field name=\"%s\" type=\"%s\"/>",
> + vec_lanes[i].suffix, ts->str);
> + }
Really? Separate 128-bit registers for each Zreg lane?
Surely that's not what gdb does...
r~
