On 10/14/19 3:49 AM, Alex Bennée wrote: > @@ -190,14 +211,18 @@ static uint64_t * find_counter(struct qemu_plugin_insn > *insn) > uint32_t opcode; > InsnClassExecCount *class = NULL; > > - /* we expect all instructions to by 32 bits for ARM */ > - g_assert(qemu_plugin_insn_size(insn) == 4); > + /* > + * We only match the first 32 bits of the instruction which is > + * fine for most RISCs but a bit limiting for CISC architectures. > + * They would probably benefit from a more tailored plugin. > + * However we can fall back to individual instruction counting. > + */ > opcode = *((uint32_t *)qemu_plugin_insn_data(insn));
This totally ignores the endianness of the host. I'm not keen on reading more than the number of bytes in the insn either... r~
