This unifies the implementation of the actual instructions for
a32, t32, and t16.
This has been tested by running the debian 9 armhf installer,
which does a far amount of switching between arm and thumb modes.
I've also run Peter's ARM TFM image, and all of the existing
RISU tests that we have. (Our RISU test cases are nowhere near
complete for 32-bit mode, but it did find 3 bugs, so not useless.)
Based-on: 20190819151743.17267-1-richard.hender...@linaro.org
"[PULL 0/3] decodetree improvements"
Changes from v1:
* Lots of prep patches merged.
* Lots of patches split into smaller bits.
Which is why this patch set is larger than v1 despite the merge.
* Do not use STREG_EXC_RET in Hyp mode (patch 3).
* Map more UNPREDICTABLE to UNDEF in LDM/STM (patches 28-30).
* Split gen_nop_hint (patch 59).
* Do not move single-step check to gen_goto_tb, but do simplify
gen_jmp by inlining gen_bx_im (patch 68).
r~
Richard Henderson (68):
target/arm: Use store_reg_from_load in thumb2 code
target/arm: Add stubs for aa32 decodetree
target/arm: Convert Data Processing (register)
target/arm: Convert Data Processing (reg-shifted-reg)
target/arm: Convert Data Processing (immediate)
target/arm: Convert multiply and multiply accumulate
target/arm: Simplify UMAAL
target/arm: Convert Saturating addition and subtraction
target/arm: Convert Halfword multiply and multiply accumulate
target/arm: Simplify op_smlaxxx for SMLAL*
target/arm: Simplify op_smlawx for SMLAW*
target/arm: Convert MSR (immediate) and hints
target/arm: Convert MRS/MSR (banked, register)
target/arm: Convert Cyclic Redundancy Check
target/arm: Convert BX, BXJ, BLX (register)
target/arm: Convert CLZ
target/arm: Convert ERET
target/arm: Convert the rest of A32 Miscelaneous instructions
target/arm: Convert T32 ADDW/SUBW
target/arm: Convert load/store (register, immediate, literal)
target/arm: Convert Synchronization primitives
target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
target/arm: Convert Parallel addition and subtraction
target/arm: Convert Packing, unpacking, saturation, and reversal
target/arm: Convert Signed multiply, signed and unsigned divide
target/arm: Convert MOVW, MOVT
target/arm: Convert LDM, STM
target/arm: Diagnose writeback register in list for LDM for v7
target/arm: Diagnose too few registers in list for LDM/STM
target/arm: Diagnose base == pc for LDM/STM
target/arm: Convert B, BL, BLX (immediate)
target/arm: Convert SVC
target/arm: Convert RFE and SRS
target/arm: Convert Clear-Exclusive, Barriers
target/arm: Convert CPS (privileged)
target/arm: Convert SETEND
target/arm: Convert PLI, PLD, PLDW
target/arm: Convert Unallocated memory hint
target/arm: Convert Table Branch
target/arm: Convert SG
target/arm: Convert TT
target/arm: Simplify disas_thumb2_insn
target/arm: Simplify disas_arm_insn
target/arm: Add skeleton for T16 decodetree
target/arm: Convert T16 data-processing (two low regs)
target/arm: Convert T16 load/store (register offset)
target/arm: Convert T16 load/store (immediate offset)
target/arm: Convert T16 add pc/sp (immediate)
target/arm: Convert T16 load/store multiple
target/arm: Convert T16 add/sub (3 low, 2 low and imm)
target/arm: Convert T16 one low register and immediate
target/arm: Convert T16 branch and exchange
target/arm: Convert T16 add, compare, move (two high registers)
target/arm: Convert T16 adjust sp (immediate)
target/arm: Convert T16, extract
target/arm: Convert T16, Change processor state
target/arm: Convert T16, Reverse bytes
target/arm: Convert T16, nop hints
target/arm: Split gen_nop_hint
target/arm: Convert T16, push and pop
target/arm: Convert T16, Conditional branches, Supervisor call
target/arm: Convert T16, Miscellaneous 16-bit instructions
target/arm: Convert T16, shift immediate
target/arm: Convert T16, load (literal)
target/arm: Convert T16, Unconditional branch
target/arm: Convert T16, long branches
target/arm: Clean up disas_thumb_insn
target/arm: Inline gen_bx_im into callers
target/arm/translate.c | 7068 ++++++++++++++--------------------
target/arm/Makefile.objs | 24 +
target/arm/a32-uncond.decode | 74 +
target/arm/a32.decode | 534 +++
target/arm/t16.decode | 279 ++
target/arm/t32.decode | 629 +++
6 files changed, 4536 insertions(+), 4072 deletions(-)
create mode 100644 target/arm/a32-uncond.decode
create mode 100644 target/arm/a32.decode
create mode 100644 target/arm/t16.decode
create mode 100644 target/arm/t32.decode
--
2.17.1
