On 8/16/19 11:59 PM, Aleksandar Markovic wrote: >> From: "Paul A. Clarke" <p...@us.ibm.com> ... >> ISA 3.0B has xscvdpspn leaving its result in word 1 of the target > register, >> and mffprwz expecting its input to come from word 0 of the source > register. >> This sequence fails with QEMU, as a shift is required between those two >> instructions. However, the hardware splats the result to both word 0 > and >> word 1 of its output register, so the shift is not necessary. >> Expect a future revision of the ISA to specify this behavior. >> > > Hmmm... Isn't this a gcc bug (using undocumented hardware feature), given > everything you said here?
The key here is "expect a future revision of the ISA to specify this behavior". It's clearly within IBM's purview to adjust the specification to document a previously undocumented hardware feature. r~
