Hi Palmer,
On Wed, Aug 7, 2019 at 10:53 AM Bin Meng <bmeng...@gmail.com> wrote:
>
> On Wed, Aug 7, 2019 at 5:06 AM Philippe Mathieu-Daudé <phi...@redhat.com>
> wrote:
> >
> > On 8/5/19 8:43 AM, Bin Meng wrote:
> > > On Mon, Aug 5, 2019 at 2:14 PM Chih-Min Chao <chihmin.c...@sifive.com>
> > > wrote:
> > >> On Sat, Aug 3, 2019 at 8:27 AM Bin Meng <bmeng...@gmail.com> wrote:
> > >>>
> > >>> Some of the SoC IP block sizes are wrong. Correct them according
> > >>> to the FE310 manual.
> > >>>
> > >>> Signed-off-by: Bin Meng <bmeng...@gmail.com>
> > >>> ---
> > >>>
> > >>> hw/riscv/sifive_e.c | 6 +++---
> > >>> 1 file changed, 3 insertions(+), 3 deletions(-)
> > >>>
> > >>> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > >>> index 2a499d8..9655847 100644
> > >>> --- a/hw/riscv/sifive_e.c
> > >>> +++ b/hw/riscv/sifive_e.c
> > >>> @@ -53,13 +53,13 @@ static const struct MemmapEntry {
> > >>> hwaddr base;
> > >>> hwaddr size;
> > >>> } sifive_e_memmap[] = {
> > >>> - [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
> > >>> + [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
> > >>> [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
> > >>> [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
> > >>> [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
> > >>> [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
> > >>> - [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
> > >>> - [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
> > >>> + [SIFIVE_E_AON] = { 0x10000000, 0x1000 },
> > >>> + [SIFIVE_E_PRCI] = { 0x10008000, 0x1000 },
> > >>> [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
> > >>> [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
> > >>> [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
> > >>> --
> > >>> 2.7.4
> > >>>
> > >>
> > >> It seems the modification follows E310-G002(Hifive1 Rev B) spec and the
> > >> origin is for E310-G000(Hifive1) spec.
> > >> There should be some way to specify different board version with
> > >> different memory map or we have policy, always support the latest spec.
> >
> > I agree with Chao, it would be cleaner to have two different boards
> > (machines).
> > Since the SoCs are very similar, you could add a 'revision' property and
> > use it to select the correct map.
> >
>
> I am not sure if adding two different machines will bring us a lot of
> benefits, since the only difference is the SoC revision with different
> block sizes.
>
> > >>
> > >
> > > Yes, I checked both specs. The older spec says these bigger sizes,
> > > however their register sizes fit well in the smaller range as well. So
> > > I think the modification works well for both.
> >
> > This is OK for the PRCI, since sifive_prci_create() does not use
> > memmap[SIFIVE_E_PRCI].size.
> >
> > However the AON case is borderline, since you shrink it from 32KiB to 4KiB.
> >
>
> AON is not implemented anyway currently. And I checked the FE310 old
> spec, its register block size is still within the 4KiB range, so
> shrinking the size should be fine for both old and new SoC.
>
> > BTW (not related to this patch) it is odd a function named
> > sifive_mmio_emulate() creates a RAM region with memory_region_init_ram()
> > and does not use the UnimplementedDevice (see make_unimp_dev() in
> > hw/arm/musca.c).
> >
What's your suggestion regarding this patch?
Regards,
Bin
