On Fri, Aug 2, 2019 at 5:27 PM Bin Meng <bmeng...@gmail.com> wrote:
>
> Some of the SoC IP block sizes are wrong. Correct them according
> to the FE310 manual.
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_e.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 2a499d8..9655847 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -53,13 +53,13 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } sifive_e_memmap[] = {
> - [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
> + [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
> [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
> [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
> [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
> [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
> - [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
> - [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
> + [SIFIVE_E_AON] = { 0x10000000, 0x1000 },
> + [SIFIVE_E_PRCI] = { 0x10008000, 0x1000 },
> [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
> [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
> [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
> --
> 2.7.4
>
>
