This is a v2 of the patch series posted in [1]. Patches 1-9 are just cleanups; patches 10-39 are something actually interesting. Compared to v1, I started using preprocessor more extensively to generate repetitive boilerplate code; opinions/alternatives are welcome and appreciated.
I tried to eliminate as many errors reported by scripts/checkpatch.pl as I could, but there are still some left; AFAICT they appear to be non-applicable false positives caused by preprocessor macros. There is a known flaw of M* operands documented in patches 25 and 39; it will be addressed in v3. (It has some design implications which require larger changes, so that's why I'm not including them right away, but I already have a good idea of how to address this.) Cheers, -Jan Changes from v1: There is in fact little overlap with v1, apart from the minor cleanup patches; I tried a different approach this time. References: 1. https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg07041.html Jan Bobek (36): target/i386: reduce scope of variable aflag target/i386: use dflag from DisasContext target/i386: use prefix from DisasContext target/i386: use pc_start from DisasContext target/i386: make variable b1 const target/i386: make variable is_xmm const target/i386: add vector register file alignment constraints target/i386: introduce gen_(ld,st)d_env_A0 target/i386: introduce gen_sse_ng target/i386: disable unused function warning temporarily target/i386: introduce mnemonic aliases for several gvec operations target/i386: introduce function ck_cpuid target/i386: introduce instruction operand infrastructure target/i386: introduce helpers for decoding modrm fields target/i386: introduce modifier for direct-only operand decoding target/i386: introduce generic operand alias target/i386: introduce generic load-store operand target/i386: introduce insn.h target/i386: introduce code generators target/i386: introduce instruction translator macros target/i386: introduce Ib (immediate) operand target/i386: introduce M* (memptr) operands target/i386: introduce G*, R*, E* (general register) operands target/i386: introduce RdMw operand target/i386: introduce P*, N*, Q* (MMX) operands target/i386: introduce helper-based code generator macros target/i386: introduce gvec-based code generator macros target/i386: introduce MMX translators target/i386: introduce MMX code generators target/i386: introduce MMX instructions to insn.h target/i386: introduce V*, U*, W* (SSE/AVX) operands target/i386: introduce UdqMq operand target/i386: introduce SSE translators target/i386: introduce SSE code generators target/i386: introduce SSE instructions to insn.h target/i386: introduce memory-pointer operand read/write workarounds Richard Henderson (3): target/i386: Push rex_r into DisasContext target/i386: Push rex_w into DisasContext target/i386: Simplify gen_exception arguments target/i386/cpu.h | 6 +- target/i386/insn.h | 381 ++++++++ target/i386/translate.c | 2032 ++++++++++++++++++++++++++++++++------- 3 files changed, 2095 insertions(+), 324 deletions(-) create mode 100644 target/i386/insn.h -- 2.20.1
