On Thu, Jun 20, 2019 at 10:37:31PM +0800, Kirti Wankhede wrote:
> These functions save and restore PCI device specific data - config
> space of PCI device.
> Tested save and restore with MSI and MSIX type.
>
> Signed-off-by: Kirti Wankhede <kwankh...@nvidia.com>
> Reviewed-by: Neo Jia <c...@nvidia.com>
> ---
> hw/vfio/pci.c | 112
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/vfio/pci.h | 29 +++++++++++++++
> 2 files changed, 141 insertions(+)
>
> diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
> index ce3fe96efe2c..09a0821a5b1c 100644
> --- a/hw/vfio/pci.c
> +++ b/hw/vfio/pci.c
> @@ -1187,6 +1187,118 @@ void vfio_pci_write_config(PCIDevice *pdev,
> }
> }
>
> +void vfio_pci_save_config(VFIODevice *vbasedev, QEMUFile *f)
> +{
> + VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
> + PCIDevice *pdev = &vdev->pdev;
> + uint16_t pci_cmd;
> + int i;
> +
> + for (i = 0; i < PCI_ROM_SLOT; i++) {
> + uint32_t bar;
> +
> + bar = pci_default_read_config(pdev, PCI_BASE_ADDRESS_0 + i * 4, 4);
> + qemu_put_be32(f, bar);
> + }
> +
> + qemu_put_be32(f, vdev->interrupt);
> + if (vdev->interrupt == VFIO_INT_MSI) {
> + uint32_t msi_flags, msi_addr_lo, msi_addr_hi = 0, msi_data;
> + bool msi_64bit;
> +
> + msi_flags = pci_default_read_config(pdev, pdev->msi_cap +
> PCI_MSI_FLAGS,
> + 2);
> + msi_64bit = (msi_flags & PCI_MSI_FLAGS_64BIT);
> +
> + msi_addr_lo = pci_default_read_config(pdev,
> + pdev->msi_cap + PCI_MSI_ADDRESS_LO,
> 4);
> + qemu_put_be32(f, msi_addr_lo);
> +
> + if (msi_64bit) {
> + msi_addr_hi = pci_default_read_config(pdev,
> + pdev->msi_cap +
> PCI_MSI_ADDRESS_HI,
> + 4);
> + }
> + qemu_put_be32(f, msi_addr_hi);
> +
> + msi_data = pci_default_read_config(pdev,
> + pdev->msi_cap + (msi_64bit ? PCI_MSI_DATA_64 :
> PCI_MSI_DATA_32),
> + 2);
> + qemu_put_be32(f, msi_data);
> + } else if (vdev->interrupt == VFIO_INT_MSIX) {
> + uint16_t offset;
> +
> + /* save enable bit and maskall bit */
> + offset = pci_default_read_config(pdev,
> + pdev->msix_cap + PCI_MSIX_FLAGS + 1,
> 2);
> + qemu_put_be16(f, offset);
> + msix_save(pdev, f);
> + }
> + pci_cmd = pci_default_read_config(pdev, PCI_COMMAND, 2);
> + qemu_put_be16(f, pci_cmd);
> +}
> +
> +void vfio_pci_load_config(VFIODevice *vbasedev, QEMUFile *f)
> +{
> + VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
> + PCIDevice *pdev = &vdev->pdev;
> + uint32_t interrupt_type;
> + uint32_t msi_flags, msi_addr_lo, msi_addr_hi = 0, msi_data;
> + uint16_t pci_cmd;
> + bool msi_64bit;
> + int i;
> +
> + /* retore pci bar configuration */
> + pci_cmd = pci_default_read_config(pdev, PCI_COMMAND, 2);
> + vfio_pci_write_config(pdev, PCI_COMMAND,
> + pci_cmd & (!(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)),
> 2);
> + for (i = 0; i < PCI_ROM_SLOT; i++) {
> + uint32_t bar = qemu_get_be32(f);
> +
> + vfio_pci_write_config(pdev, PCI_BASE_ADDRESS_0 + i * 4, bar, 4);
> + }
> + vfio_pci_write_config(pdev, PCI_COMMAND,
> + pci_cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY, 2);
> +
> + interrupt_type = qemu_get_be32(f);
> +
> + if (interrupt_type == VFIO_INT_MSI) {
> + /* restore msi configuration */
> + msi_flags = pci_default_read_config(pdev,
> + pdev->msi_cap + PCI_MSI_FLAGS,
> 2);
> + msi_64bit = (msi_flags & PCI_MSI_FLAGS_64BIT);
> +
> + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_FLAGS,
> + msi_flags & (!PCI_MSI_FLAGS_ENABLE), 2);
> +
> + msi_addr_lo = qemu_get_be32(f);
> + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_LO,
> + msi_addr_lo, 4);
> +
> + msi_addr_hi = qemu_get_be32(f);
> + if (msi_64bit) {
> + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_HI,
> + msi_addr_hi, 4);
> + }
> + msi_data = qemu_get_be32(f);
> + vfio_pci_write_config(pdev,
> + pdev->msi_cap + (msi_64bit ? PCI_MSI_DATA_64 :
> PCI_MSI_DATA_32),
> + msi_data, 2);
> +
> + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_FLAGS,
> + msi_flags | PCI_MSI_FLAGS_ENABLE, 2);
> + } else if (interrupt_type == VFIO_INT_MSIX) {
> + uint16_t offset = qemu_get_be16(f);
> +
> + /* load enable bit and maskall bit */
> + vfio_pci_write_config(pdev, pdev->msix_cap + PCI_MSIX_FLAGS + 1,
> + offset, 2);
> + msix_load(pdev, f);
> + }
> + pci_cmd = qemu_get_be16(f);
> + vfio_pci_write_config(pdev, PCI_COMMAND, pci_cmd, 2);
> +}
> +
per the previous discussion, pci config state save/restore are better
defined in fileds of VMStateDescription.
> /*
> * Interrupt setup
> */
> diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h
> index 834a90d64686..847be5f56478 100644
> --- a/hw/vfio/pci.h
> +++ b/hw/vfio/pci.h
> @@ -19,6 +19,7 @@
> #include "qemu/queue.h"
> #include "qemu/timer.h"
>
> +#ifdef CONFIG_LINUX
> #define PCI_ANY_ID (~0)
>
> struct VFIOPCIDevice;
> @@ -202,4 +203,32 @@ void vfio_display_reset(VFIOPCIDevice *vdev);
> int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
> void vfio_display_finalize(VFIOPCIDevice *vdev);
>
> +void vfio_pci_save_config(VFIODevice *vbasedev, QEMUFile *f);
> +void vfio_pci_load_config(VFIODevice *vbasedev, QEMUFile *f);
> +
> +static inline Object *vfio_pci_get_object(VFIODevice *vbasedev)
> +{
> + VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
> +
> + return OBJECT(vdev);
> +}
> +
> +#else
> +static inline void vfio_pci_save_config(VFIODevice *vbasedev, QEMUFile *f)
> +{
> + g_assert(false);
> +}
> +
> +static inline void vfio_pci_load_config(VFIODevice *vbasedev, QEMUFile *f)
> +{
> + g_assert(false);
> +}
> +
> +static inline Object *vfio_pci_get_object(VFIODevice *vbasedev)
> +{
> + return NULL;
> +}
> +
> +#endif
> +
> #endif /* HW_VFIO_VFIO_PCI_H */
> --
> 2.7.0
>
