On Sat, 25 May 2019 at 15:14, Cédric Le Goater <c...@kaod.org> wrote: > > The FMC controller on the Aspeed SoCs support DMA to access the flash > modules. It can operate in a normal mode, to copy to or from the flash > module mapping window, or in a checksum calculation mode, to evaluate > the best clock settings for reads. > > The model introduces two custom address spaces for DMAs: one for the > AHB window of the FMC flash devices and one for the DRAM. The latter > is populated using a "dram" link set from the machine with the RAM > container region. > > Signed-off-by: Cédric Le Goater <c...@kaod.org>
Cédric is our flash controller expert. This looks good as far as I can tell. Acked-by: Joel Stanley <j...@jms.id.au>
