On Sat, 25 May 2019 at 15:14, Cédric Le Goater <c...@kaod.org> wrote: > > The RAM memory region is defined after the SoC is realized when the > SDMC controller has cheched that the defined RAM size for the machine
checked > is correct. This is problematic for controller models requiring a link > on the RAM region, for DMA support in the SMC controller for instance. > > Introduce a container memory region for the RAM that we can link into > the controllers early, before the SoC is realized. It will be > populated with the RAM region after the checks have be done. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Joel Stanley <j...@jms.id.au>
