Interrupts are disabled in PALmode, and when the PS IL is
high enough. We don't actually get the interrupt levels
correct yet; settle for interrupts enabled only at IL0.
Signed-off-by: Richard Henderson <r...@twiddle.net>
---
cpu-exec.c | 16 +++++++++++++---
target-alpha/exec.h | 7 ++++++-
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 5d6c9a8..68c3d1d 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -529,9 +529,19 @@ int cpu_exec(CPUState *env1)
next_tb = 0;
}
#elif defined(TARGET_ALPHA)
- if (interrupt_request & CPU_INTERRUPT_HARD) {
- do_interrupt(env);
- next_tb = 0;
+ if (env->pal_mode == 0 && (env->ps & PS_INT_MASK) == 0) {
+ int idx = -1;
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ idx = EXCP_DEV_INTERRUPT;
+ }
+ if (interrupt_request & CPU_INTERRUPT_TIMER) {
+ idx = EXCP_CLK_INTERRUPT;
+ }
+ if (idx >= 0) {
+ env->exception_index = idx;
+ do_interrupt(env);
+ next_tb = 0;
+ }
}
#elif defined(TARGET_CRIS)
if (interrupt_request & CPU_INTERRUPT_HARD
diff --git a/target-alpha/exec.h b/target-alpha/exec.h
index 6ae96d1..a504758 100644
--- a/target-alpha/exec.h
+++ b/target-alpha/exec.h
@@ -39,7 +39,12 @@ register struct CPUAlphaState *env asm(AREG0);
static inline int cpu_has_work(CPUState *env)
{
- return (env->interrupt_request & CPU_INTERRUPT_HARD);
+ /* ??? There's a model-specific mapping between external hardware
+ interrupt numbers and the Unix PALcode interrupt levels. */
+ int req = CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER;
+ return ((env->interrupt_request & req)
+ && env->pal_mode == 0
+ && (env->ps & PS_INT_MASK) == 0);
}
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
--
1.7.3.4
