Hi Peter,
please pull the following batch of updates to target/xtensa:
The following changes since commit efb4f3b62c69383a7308d7b739a3193e7c0ccae8:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into
staging (2019-05-10 14:49:36 +0100)
are available in the git repository at:
git://github.com/OSLL/qemu-xtensa.git tags/20190520-xtensa
for you to fetch changes up to b345e140534ea17814b02bdf8798f18db6295304:
target/xtensa: implement exclusive access option (2019-05-15 10:31:52 -0700)
----------------------------------------------------------------
target/xtensa: SR reorganization and options for modern cores
Reorganize special register handling to support configurations with
conflicting SR definitions.
Implement options used by the modern xtensa cores:
- memory protection unit;
- block prefetch;
- exclusive access
Add special register definitions and IRQ types for ECC/parity,
gather/scatter and IDMA.
----------------------------------------------------------------
Max Filippov (9):
target/xtensa: get rid of centralized SR properties
target/xtensa: make internal MMU functions static
target/xtensa: define IDMA and gather/scatter IRQ types
target/xtensa: add parity/ECC option SRs
target/xtensa: implement MPU option
target/xtensa: implement DIWBUI.P opcode
target/xtensa: implement block prefetch option opcodes
target/xtensa: update list of exception causes
target/xtensa: implement exclusive access option
target/xtensa/cpu.c | 2 +-
target/xtensa/cpu.h | 58 +-
target/xtensa/helper.c | 1 +
target/xtensa/helper.h | 6 +
target/xtensa/mmu_helper.c | 532 ++++++-
target/xtensa/op_helper.c | 42 +
target/xtensa/overlay_tool.h | 43 +-
target/xtensa/translate.c | 2951 ++++++++++++++++++++++++-------------
tests/tcg/xtensa/test_exclusive.S | 48 +
9 files changed, 2574 insertions(+), 1109 deletions(-)
create mode 100644 tests/tcg/xtensa/test_exclusive.S
--
Thanks.
-- Max
