On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote:
> At present the PLIC is instantiated to support only one hart, while
> the machine allows at most 4 harts to be created. When more than 1
> hart is configured, PLIC needs to instantiated to support multicore,
> otherwise an SMP OS does not work.
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index e2120ac..a416d5d 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -344,6 +344,8 @@ static void
> riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
> + char *plic_hart_config;
> + size_t plic_hart_config_len;
> int i;
> Error *err = NULL;
> NICInfo *nd = &nd_table[0];
> @@ -357,9 +359,21 @@ static void
> riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(system_memory,
> memmap[SIFIVE_U_MROM].base,
> mask_rom);
>
> + /* create PLIC hart topology configuration string */
> + plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
> smp_cpus;
> + plic_hart_config = g_malloc0(plic_hart_config_len);
> + for (i = 0; i < smp_cpus; i++) {
> + if (i != 0) {
> + strncat(plic_hart_config, ",", plic_hart_config_len);
> + }
> + strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
> + plic_hart_config_len);
> + plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) +
> 1);
> + }
> +
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
> - (char *)SIFIVE_U_PLIC_HART_CONFIG,
> + plic_hart_config,
> SIFIVE_U_PLIC_NUM_SOURCES,
> SIFIVE_U_PLIC_NUM_PRIORITIES,
> SIFIVE_U_PLIC_PRIORITY_BASE,
