The SSE-200 hardware has configurable integration settings which
determine whether its two CPUs have the FPU and DSP:
* CPU0_FPU (default 0)
* CPU0_DSP (default 0)
* CPU1_FPU (default 1)
* CPU1_DSP (default 1)
Similarly, the IoTKit has settings for its single CPU:
* CPU0_FPU (default 1)
* CPU0_DSP (default 1)
Of our four boards that use either the IoTKit or the SSE-200:
* mps2-an505, mps2-an521 and musca-a use the default settings
* musca-b1 enables FPU and DSP on both CPUs
Currently QEMU models all these boards using CPUs with
both FPU and DSP enabled. This means that we are incorrect
for mps2-an521 and musca-a, which should not have FPU or DSP
on CPU0.
This patchset fixes this (fairly minor) inaccuracy by
implementing properties on the CPU to disable the relevant
CPU features and then wiring them up through the armv7m
object and the ARMSSE SoC container object, so that our
IotKit and SSE200 models behave by default the same way as
the hardware default does, and our Musca-B1 board model
forces the FPU/DSP to be present on CPU, as the hardware does.
The 'neon' property is not strictly required for the M-profile
issues described above, but I implemented it on the CPU
object because disable-neon and disable-vfp interact
for A-profile CPUs.
thanks
-- PMM
Peter Maydell (4):
target/arm: Allow VFP and Neon to be disabled via a CPU property
target/arm: Allow M-profile CPUs to disable the DSP extension via CPU
property
hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU
hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards
include/hw/arm/armsse.h | 7 ++
include/hw/arm/armv7m.h | 4 +
target/arm/cpu.h | 6 ++
hw/arm/armsse.c | 58 ++++++++++---
hw/arm/armv7m.c | 18 ++++
hw/arm/musca.c | 8 ++
target/arm/cpu.c | 179 ++++++++++++++++++++++++++++++++++++++--
7 files changed, 262 insertions(+), 18 deletions(-)
--
2.20.1
