On Fri, May 03, 2019 at 03:53:06PM +1000, Suraj Jitindar Singh wrote: > The Access Segment Descriptor Register (ASDR) provides information about > the storage element when taking a hypervisor storage interrupt. When > performing nested radix address translation, this is normally the guest > real address. This register is present on POWER9 processors and later. > > Implement the ADSR, note read and write access is limited to the > hypervisor. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>
Reviewed-by: David Gibson <da...@gibson.dropbear.id.au>
> ---
> target/ppc/cpu.h | 1 +
> target/ppc/translate_init.inc.c | 6 ++++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 19b3e1de0e..8d66265e5a 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1797,6 +1797,7 @@ void ppc_compat_add_property(Object *obj, const char
> *name,
> #define SPR_MPC_MD_DBRAM1 (0x32A)
> #define SPR_RCPU_L2U_RA3 (0x32B)
> #define SPR_TAR (0x32F)
> +#define SPR_ASDR (0x330)
> #define SPR_IC (0x350)
> #define SPR_VTB (0x351)
> #define SPR_MMCRC (0x353)
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 9cd33e79ef..a0cae58e19 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -8243,6 +8243,12 @@ static void gen_spr_power9_mmu(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_ptcr,
> KVM_REG_PPC_PTCR, 0x00000000);
> + /* Address Segment Descriptor Register */
> + spr_register_hv(env, SPR_ASDR, "ASDR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x0000000000000000);
> #endif
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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