On 4/16/19 5:57 AM, Peter Maydell wrote: > The M-profile floating point support has three associated config > registers: FPCAR, FPCCR and FPDSCR. It also makes the registers > CPACR and NSACR have behaviour other than reads-as-zero. > Add support for all of these as simple reads-as-written registers. > We will hook up actual functionality later. > > The main complexity here is handling the FPCCR register, which > has a mix of banked and unbanked bits. > > Note that we don't share storage with the A-profile > cpu->cp15.nsacr and cpu->cp15.cpacr_el1, though the behaviour > is quite similar, for two reasons: > * the M profile CPACR is banked between security states > * it preserves the invariant that M profile uses no state > inside the cp15 substruct > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu.h | 34 ++++++++++++ > hw/intc/armv7m_nvic.c | 125 ++++++++++++++++++++++++++++++++++++++++++ > target/arm/cpu.c | 5 ++ > target/arm/machine.c | 16 ++++++ > 4 files changed, 180 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
