On 3/12/19 3:30 AM, gengdongjiu wrote: > From: Dongjiu Geng <gengdong...@huawei.com> > > Some generic arch timer registers are Config-RW in the EL0, > which means the EL0 exception level can have write permission > if it is appropriately configured. > > When VM access registers, it firstly checks whether they have RW > permission, then check whether it is appropriately configured. > If they are defined to Ready only in EL0, even though they have been > appropriately configured, they still do not have write permission. > So need to add the write permission according to ARMV8 spec when > define it. > > Signed-off-by: Dongjiu Geng <gengdong...@huawei.com> > --- > When VM kernel or Hypervisor configures the timer registers to RW in EL0 > user space, it will still have below panic when EL0 user space access > the timer registers. > > [INFO ]@(el0_sync:60): UNIMPLEMENTED, esr=2000000 > [INFO ]@(unimpl_exception:88): KERNEL UNIMPLEMENTED EXCEPTION > [INFO ]@(unimpl_exception:98): FAR=0000000000000000, ESR=02000000 (EC=0x0, > IL=0x1, ISS=0x0) > [INFO ]@(dump_registers:64): KERNEL REGISTERS > [INFO ]@(dump_registers:68): X0=00000000f52b7d50 X1=00000000040d5040 > [INFO ]@(dump_registers:68): X2=0000004000033e10 X3=0000000000000000 > [INFO ]@(dump_registers:68): X4=000000007fffffff X5=0000000000000020 > [INFO ]@(dump_registers:68): X6=0000000000000020 X7=000000000c00b030 > --- > target/arm/helper.c | 30 +++++++++++++++--------------- > 1 file changed, 15 insertions(+), 15 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
