On 2/12/19 11:52 AM, Peter Maydell wrote:
> In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
> the ARMSSE, we set up the wiring of the expansion IRQs via nested
> loops: the outer loop on 'i' loops for each CPU, and the inner loop
> on 'j' loops for each interrupt. Fix a typo which meant we were
> wiring every expansion IRQ line to external IRQ 0 on CPU 0 and
> to external IRQ 1 on CPU 1.
>
> Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration")
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@redhat.com>
> ---
> It turns out that the ARM-TFM image I was using to test that
> I hadn't broken the mps2-an505 doesn't actually rely on any
> interrupts from the external devices...
How did you notice that, simply reviewing? Via 'info qtree'?
>
> hw/arm/armsse.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index 5d53071a5a0..9a8c49547db 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -565,7 +565,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up
> */
> s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);
> for (j = 0; j < s->exp_numirq; j++) {
> - s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, i + 32);
> + s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32);
> }
> if (i == 0) {
> gpioname = g_strdup("EXP_IRQ");
>
