On Tue, 12 Feb 2019 at 11:05, Philippe Mathieu-Daudé <phi...@redhat.com> wrote:
>
> On 2/12/19 11:52 AM, Peter Maydell wrote:
> > In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
> > the ARMSSE, we set up the wiring of the expansion IRQs via nested
> > loops: the outer loop on 'i' loops for each CPU, and the inner loop
> > on 'j' loops for each interrupt. Fix a typo which meant we were
> > wiring every expansion IRQ line to external IRQ 0 on CPU 0 and
> > to external IRQ 1 on CPU 1.
> >
> > Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration")
> >
> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
>
> Reviewed-by: Philippe Mathieu-Daudé <phi...@redhat.com>
>
> > ---
> > It turns out that the ARM-TFM image I was using to test that
> > I hadn't broken the mps2-an505 doesn't actually rely on any
> > interrupts from the external devices...
>
> How did you notice that, simply reviewing? Via 'info qtree'?I'm working on a model of a different board (Musca) which also uses the SSE-200, and the test code I had for that does happen to care about the interrupts. thanks -- PMM
