On 1/21/19 10:51 AM, Peter Maydell wrote: > The SSE-200 has two Cortex-M33 CPUs. These see the same view > of memory, with the exception of the "private CPU region" which > has per-CPU devices. Internal device interrupts for SSE-200 > devices are mostly wired up to both CPUs, with the exception of > a few per-CPU devices. External GPIO inputs on the SSE-200 > device are provided for the second CPU's interrupts above 32, > as is already the case for the first CPU. > > Refactor the code to support creation of multiple CPUs. > For the moment we leave all CPUs with the same view of > memory: this will not work in the multiple-CPU case, but > we will fix this in the following commit. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > include/hw/arm/armsse.h | 21 +++- > hw/arm/armsse.c | 206 ++++++++++++++++++++++++++++++++-------- > 2 files changed, 180 insertions(+), 47 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
