On Mon, Nov 19, 2018 at 3:35 AM Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > > On Mon, Nov 19, 2018 at 12:08 PM Peter Maydell <peter.mayd...@linaro.org> > wrote: > > On 19 November 2018 at 10:43, Philippe Mathieu-Daudé <f4...@amsat.org> > > wrote: > > > Hi Seth, > > > > > > On Mon, Nov 19, 2018 at 4:17 AM Seth K <skint...@gmail.com> wrote: > > >> > > >> From: Seth Kintigh <skint...@gmail.com> > > >> > > >> I corrected these 2 memory regions based on specifications from the chip > > >> manufacturer. The existing ranges seem to overlap and and cause odd > > >> behavior and/or crashes when trying to set up multiple UARTs, > > >> > > >> Signed-off-by: Seth Kintigh <skint...@gmail.com> > > >> --- > > >> Phil, I hope this is the right format. > > > > > > Better but still incorrect. > > > > What Phil says below is true, but since this is a simple > > patch I have applied it by hand to my target-arm.next branch, > > so it will go into the next release of QEMU. Thanks for your > > contribution! (I rewrote the commit message a bit to make > > it fit in with the usual style we use for our commit messages; > > I hope that's OK.) > > Thanks Peter! > > You can also add: > Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> > Tested-by: Philippe Mathieu-Daudé <f4...@amsat.org> > > Regards,
Thanks for applying this Peter and thanks for the patch Seth. Alistair > > Phil. > > > > > > I tried to apply your patch but get an error: > > > > > > $ git am seth_stm32f2xx_regsize.mbox > > > > I suspect this is because the email is in dual text/HTML format. > > > > thanks > > -- PMM >
