This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with some patches ontop.
This has been slightly tested and can run other architecture softmmu code for a number of instructions but eventually QEMU will either seg fault or generate an illigal instruction (depending on the guest architecture). I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it. I'll test both a lot more before I send a full patchset. My hope of submitting an RFC is that some extra eyes on the code might help catch what is wrong. Comparing the guest CPU state to a working version hasn't given any hints as the states match, even up until the generated code segfaults. This branch can be found here: https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend-upstream.next The working version with Michael's orignal patch and work ontop can be found here: https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend.next Alistair Francis (23): elf.h: Add the RISCV ELF magic numbers linux-user: Add host dependency for RISC-V 32-bit linux-user: Add host dependency for RISC-V 64-bit exec: Add RISC-V GCC poison macro riscv: Add the tcg-target header file riscv: Add the tcg target registers riscv: tcg-target: Regiser the JIT riscv: tcg-target: Add support for the constraints riscv: tcg-target: Add the immediate encoders riscv: tcg-target: Add the instruction emitters riscv: tcg-target: Add the relocation functions riscv: tcg-target: Add the mov and movi instruction riscv: tcg-target: Add the extract instructions riscv: tcg-target: Add the out load and store instructions riscv: tcg-target: Add branch and jump instructions riscv: tcg-target: Add slowpath load and store instructions riscv: tcg-target: Add direct load and store instructions riscv: tcg-target: Add the out op decoder riscv: tcg-target: Add the prologue generation riscv: tcg-target: Add the target init code tcg: Add RISC-V cpu signal handler dias: Add RISC-V support configure: Add support for building RISC-V host accel/tcg/user-exec.c | 48 + configure | 12 +- disas.c | 10 +- include/elf.h | 55 + include/exec/poison.h | 1 + linux-user/host/riscv32/hostdep.h | 11 + linux-user/host/riscv64/hostdep.h | 11 + tcg/riscv/tcg-target.h | 173 +++ tcg/riscv/tcg-target.inc.c | 1728 +++++++++++++++++++++++++++++ 9 files changed, 2045 insertions(+), 4 deletions(-) create mode 100644 linux-user/host/riscv32/hostdep.h create mode 100644 linux-user/host/riscv64/hostdep.h create mode 100644 tcg/riscv/tcg-target.h create mode 100644 tcg/riscv/tcg-target.inc.c -- 2.19.1
