On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> @fence .... .... .... ..... ... ..... ....... %pred %succ
> @csr ............ ..... ... ..... ....... %csr %rs1
> %rd
>
> +@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=00000 %rs1
> %rd
rs2=0. This value is always parsed as decimal, not binary.
> + switch (opc) {
> + case OPC_RISC_AMOSWAP:
> + /* Note that the TCG atomic primitives are SC,
> + so we can ignore AQ/RL along this path. */
> + tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOADD:
> + tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOXOR:
> + tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOAND:
> + tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOOR:
> + tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMIN:
> + tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMAX:
> + tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMINU:
> + tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + case OPC_RISC_AMOMAXU:
> + tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
> + break;
> + default:
> + return false;
Given how these switch elements are passed in, this should use
g_assert_not_reached().
Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
