For v3, the only change is to patch 4, which is also the only patch without a reviewed-by tag.
I now check for aa64 state before checking for sve length, and added a comment about why it is important to play with sve when transitioning into aa32 state. r~ Richard Henderson (15): target/arm: Define ID_AA64ZFR0_EL1 target/arm: Adjust sve_exception_el target/arm: Pass in current_el to fp and sve_exception_el target/arm: Handle SVE vector length changes in system mode target/arm: Adjust aarch64_cpu_dump_state for system mode SVE target/arm: Clear unused predicate bits for LD1RQ target/arm: Rewrite helper_sve_ld1*_r using pages target/arm: Rewrite helper_sve_ld[234]*_r target/arm: Rewrite helper_sve_st[1234]*_r target/arm: Split contiguous loads for endianness target/arm: Split contiguous stores for endianness target/arm: Rewrite vector gather loads target/arm: Rewrite vector gather stores target/arm: Rewrite vector gather first-fault loads target/arm: Pass TCGMemOpIdx to sve memory helpers target/arm/cpu.h | 8 + target/arm/helper-sve.h | 385 +++++-- target/arm/internals.h | 5 + target/arm/cpu64.c | 42 - target/arm/helper.c | 243 +++-- target/arm/op_helper.c | 1 + target/arm/sve_helper.c | 1961 ++++++++++++++++++++++++------------ target/arm/translate-a64.c | 8 +- target/arm/translate-sve.c | 670 ++++++++---- 9 files changed, 2273 insertions(+), 1050 deletions(-) -- 2.17.1
