> From: Janeczek, Craig <jancr...@amazon.com>
> Sent: Tuesday, September 4, 2018 4:44 PM
>
> Subject: RE: [PATCH v4 3/9] target/mips: Split mips instruction handling
>
> To clarify the OPC_MUL here is not an MXU instruction, this is the original
> OPC_MUL that was in the special2 instruction set. The inclusion of this
> instruction in this switch statement is due to the suggested method of
> splitting up the mxu commands instruction handling switch statement from the
> original special2 commands.
There are five more cases where current SPECIAL2 instructions occupy free slots
in MXU opcode scheme:
/* Loongson 2F */
OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | OPC_SPECIAL2,
OPC_CLO = 0x21 | OPC_SPECIAL2,
/* Special */
OPC_SDBBP = 0x3F | OPC_SPECIAL2,
What to do with them? Should they be treated like OPC_MUL? Can you do the same
binary check as for OPC_MUL? Is there a confirmation in Ingenic gcc/asm source
for all these cases?
Thanks,
Aleksandar
