On 21 June 2018 at 02:53, Richard Henderson
<richard.hender...@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/translate-sve.c | 103 +++++++++++++++++++++++++++++++++++++
> target/arm/sve.decode | 6 +++
> 2 files changed, 109 insertions(+)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 954d6653d3..50f1ff75ef 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -3762,6 +3762,89 @@ static void do_ldr(DisasContext *s, uint32_t vofs,
> uint32_t len,
> tcg_temp_free_i64(t0);
> }
>
> +/* Similarly for stores. */
> +static void do_str(DisasContext *s, uint32_t vofs, uint32_t len,
> + int rn, int imm)
> +{
> + /* Predicate register stores can be any multiple of 2. */
> + if (len_remain) {
> + tcg_gen_ld_i64(t0, cpu_env, vofs + len_align);
> + tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align);
> +
> + switch (len_remain) {
> + case 2:
> + case 4:
> + case 8:
> + tcg_gen_qemu_st_i64(t0, addr, midx, MO_LE | ctz32(len_remain));
> + break;
> +
> + case 6:
> + tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUL);
> + tcg_gen_addi_i64(addr, addr, 4);
> + tcg_gen_shri_i64(addr, addr, 32);
Shouldn't this be shifting t0 rather than addr ?
> + tcg_gen_qemu_st_i64(t0, addr, midx, MO_LEUW);
> + break;
> +
> + default:
> + g_assert_not_reached();
> + }
> + }
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
