Hello, Here is a short series of cleanups and fixes for issues in the Aspeed SMC controller model discovered when experimenting with the MMIO exec feature and also from tests under a QEMU PowerNV machine.
Indeed, the OPAL/skiboot firmware accesses the Aspeed SoC address space using the iLPC->AHB bridge of the SuperIO controller and drives the SPI controller to access the PNOR. Thanks, C. Cédric Le Goater (3): aspeed/smc: fix dummy cycles count when in dual IO mode aspeed/smc: fix HW strapping aspeed/smc: rename aspeed_smc_flash_send_addr() to aspeed_smc_flash_setup() hw/ssi/aspeed_smc.c | 48 +++++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 23 deletions(-) -- 2.13.6
