Peter Maydell <peter.mayd...@linaro.org> writes: > The MIPS TCG target makes the assumption that the offset from the > target env pointer to the tlb_table is less than about 64K. This > used to be true, but gradual addition of features to the Arm > target means that it's no longer true there. This results in > the build-time assertion failing: > > In file included from /home/pm215/qemu/include/qemu/osdep.h:36:0, > from /home/pm215/qemu/tcg/tcg.c:28: > /home/pm215/qemu/tcg/mips/tcg-target.inc.c: In function ‘tcg_out_tlb_load’: > /home/pm215/qemu/include/qemu/compiler.h:90:36: error: static assertion > failed: "not expecting: offsetof(CPUArchState, tlb_table[NB_MMU_MODES - > 1][1]) > 0x7ff0 + 0x7fff" > #define QEMU_BUILD_BUG_MSG(x, msg) _Static_assert(!(x), msg) > ^ > /home/pm215/qemu/include/qemu/compiler.h:98:30: note: in expansion of macro > ‘QEMU_BUILD_BUG_MSG’ > #define QEMU_BUILD_BUG_ON(x) QEMU_BUILD_BUG_MSG(x, "not expecting: " #x) > ^ > /home/pm215/qemu/tcg/mips/tcg-target.inc.c:1236:9: note: in expansion of > macro ‘QEMU_BUILD_BUG_ON’ > QEMU_BUILD_BUG_ON(offsetof(CPUArchState, > ^ > /home/pm215/qemu/rules.mak:66: recipe for target 'tcg/tcg.o' failed > > An ideal long term approach would be to rearrange the CPU state > so that the tlb_table was not so far along it, but this is tricky > because it would move it from the "not cleared on CPU reset" part > of the struct to the "cleared on CPU reset" part.
Is that really a problem? Doesn't it mean we'll just reload the TLB after a reset? -- Alex Bennée
