This implements the Atomics extension, which is mandatory for v8.1. While testing the v8.2-SVE extension, I've run into issues with the GCC testsuite expecting this to exist.
Missing is the wiring up of the system registers to indicate that the extension exists, but we have no system CPU model that would exercise such a setting. r~ PS: Given the extension is mandatory, it might be better to save feature bits and file this under ARM_FEATURE_V8_1. Thoughts? PPS: Testing for this will proceed overnight. It takes a while to run the gcc testsuite and I'm ready to stop for the day. ;-) Richard Henderson (9): tcg: Introduce helpers for integer min/max target/arm: Use new min/max expanders target/xtensa: Use new min/max expanders tcg: Introduce atomic helpers for integer min/max target/riscv: Use new atomic min/max expanders target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/arm: Fill in disas_ldst_atomic target/arm: Implement CAS and CASP target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only accel/tcg/atomic_template.h | 71 +++++++++ accel/tcg/tcg-runtime.h | 8 + target/arm/cpu.h | 1 + target/arm/helper-a64.h | 2 + tcg/tcg-op.h | 50 ++++++ tcg/tcg.h | 8 + linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/helper-a64.c | 43 +++++ target/arm/translate-a64.c | 375 +++++++++++++++++++++++++++++++++++--------- target/riscv/translate.c | 72 +++------ target/xtensa/translate.c | 50 ++++-- tcg/tcg-op.c | 48 ++++++ 13 files changed, 583 insertions(+), 147 deletions(-) -- 2.14.3
