Apparently there is at least one logic bug in amongst this
set of 23 patches. I'll shout you a beer if you can find it.
I found one myself so there was probably at least two.
Hey, it boots SMP Linux here, but I think it needs more testing.
This is a series of spec conformance bug fixes and code cleanups.
We would like to get this series in after our core changes in v8.2.
* Implements WARL behavior for CSRs that don't support writes
* Improves specification conformance of the page table walker
* Change access checks from ternary operator to if statements
* Checks for misaligned PPNs
* Disallow M-mode or S-mode from fetching from User pages
* Adds reserved PTE flag check: W or W|X
* Adds prot read if mode is not U and mstatus.mxr is set
* Improves page walker comments and general readability
* Several trivial code cleanups to hw/riscv
* Replacing hard coded constants with reference to enums
or the machine memory maps.
* Adds bounds checks when writing device-tree to ROM
* Updates the cpu model to use a more modern interface
v2
- remove unused class boilerplate retains qom parent_obj
- convert cpu definition towards future model
- honor mstatus.mxr flag in page table walker
Michael Clark (23):
RISC-V: Make virt create_fdt interface consistent
RISC-V: Replace hardcoded constants with enum values
RISC-V: Make virt board description match spike
RISC-V: Use ROM base address and size from memmap
RISC-V: Remove identity_translate from load_elf
RISC-V: Mark ROM read-only after copying in code
RISC-V: Remove unused class definitions
RISC-V: Make sure rom has space for fdt
RISC-V: Include intruction hex in disassembly
RISC-V: Hold rcu_read_lock when accessing memory
RISC-V: Improve page table walker spec compliance
RISC-V: Update E order and I extension order
RISC-V: Make some header guards more specific
RISC-V: Make virt header comment title consistent
RISC-V: Use memory_region_is_ram in pte update
RISC-V: Remove EM_RISCV ELF_MACHINE indirection
RISC-V: Hardwire satp to 0 for no-mmu case
RISC-V: Remove braces from satp case statement
RISC-V: riscv-qemu port supports sv39 and sv48
RISC-V: vectored traps are optional
RISC-V: No traps on writes to misa,minstret,mcycle
RISC-V: Remove support for adhoc X_COP interrupt
RISC-V: Convert cpu definition towards future model
disas/riscv.c | 39 +++++++------
hw/riscv/sifive_clint.c | 9 +--
hw/riscv/sifive_e.c | 34 +----------
hw/riscv/sifive_u.c | 65 +++++++--------------
hw/riscv/spike.c | 65 ++++++++-------------
hw/riscv/virt.c | 77 +++++++++----------------
include/hw/riscv/sifive_clint.h | 4 ++
include/hw/riscv/sifive_e.h | 5 --
include/hw/riscv/sifive_u.h | 9 ++-
include/hw/riscv/spike.h | 15 ++---
include/hw/riscv/virt.h | 17 +++---
target/riscv/cpu.c | 125 ++++++++++++++++++++++------------------
target/riscv/cpu.h | 6 +-
target/riscv/cpu_bits.h | 3 -
target/riscv/helper.c | 65 +++++++++++++++------
target/riscv/op_helper.c | 52 ++++++++---------
16 files changed, 263 insertions(+), 327 deletions(-)
--
2.7.0
