On 01/03/18 22:53, Emilio G. Cota wrote:
[ What is this all about? See this message:
http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
Merged the separate patchsets I sent in the last couple of weeks into
one set. This will be easier to merge since it will avoid potential
merge conflicts due to adding max_insns to dc->base.
Changes since sending the separate series for sh4/sparc/mips/s390x/openrisc:
- Rebased on top of master (669743979)
- Added R-b's
- sh4: no changes since v3
- mips: no changes (no reviews yet!)
- sparc:
+ Use base.singlestep_enabled and singlestep like in other targets,
e.g. Alpha.
+ Remove the unnecessary
(dc.pc - pc_start) < (TARGET_PAGE_SIZE - 32))
check.
- s390x:
+ Remove dc->pc, use pc_next instead as David suggested.
+ Use dc for DisasContext instead of s.
+ Compute next_page in translate_insn instead of keeping it in dc.
+ Looked into dropping dc->do_debug, but don't see an easy way to do so.
- openrisc:
+ Consistently use DISAS_NORETURN after generating an
exception; fixed the two call sites that Richard pointed out,
plus a couple of others that weren't visible in the previous patch.
+ Remove the dc->next_page_start field; instead, set the max_insn
bound in translate_insn.
You can fetch this series from:
https://github.com/cota/qemu/tree/trloop-conv-v1
Diffstat below.
Thanks,
Emilio
Hi Emilio,
I don't have enough knowledge of TCG internals to review this myself,
however I can run it through my complete set of OpenBIOS test images for
qemu-system-sparc and qemu-system-sparc64 if that helps?
ATB,
Mark.
