On 02/04/2018 10:22 PM, Michael Clark wrote: > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > RISC-V code generator has complete coverage for the Base ISA v2.2, > Privileged ISA v1.9.1 and Privileged ISA v1.10: > > - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 > > Signed-off-by: Michael Clark <m...@sifive.com> > --- > target/riscv/instmap.h | 366 +++++++++ > target/riscv/translate.c | 1964 > ++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 2330 insertions(+) > create mode 100644 target/riscv/instmap.h > create mode 100644 target/riscv/translate.c
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
