On Fri, Jan 07, 2011 at 02:42:57PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/README | 14 ++++++++++++++
> tcg/tcg-op.h | 40 ++++++++++++++++++++++++++++++++++++++++
> tcg/tcg-opc.h | 6 ++++++
> tcg/tcg.c | 13 +++++++++++++
> 4 files changed, 73 insertions(+), 0 deletions(-)
>
> diff --git a/tcg/README b/tcg/README
> index 68d27ff..ef59070 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -285,6 +285,20 @@ the four high order bytes are set to zero.
> Indicate that the value of t0 won't be used later. It is useful to
> force dead code elimination.
>
> +* deposit_i32/i64 dest, t1, t2, loc
> +
> +Deposit T2 as a bitfield into T1, placing the result in DEST.
> +The bitfield is described by LOC, an immediate value:
> +
> + bits 0:7 - the length of the bitfield
> + bits 8:15 - the position of the first bit
> +
> +For example, 0x101 indicates a 1-bit field at bit 1.
> +This operation would be equivalent to
> +
> + dest = (t1 & ~2) | ((t2 << 1) & 2)
> +
> +
The encoding of the constant part actually doesn't match the one in the
C function where two arguments are separated and not encoded. What about
adding a tcg_gen_op5ii_i32/64 function and having the two arguments
separated?
Also what about a shorter name, like for example 'dep' as it is used on
some architectures.
> ********* Conditional moves
>
> * setcond_i32/i64 cond, dest, t1, t2
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 3ee0a58..c5a019a 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -2071,6 +2071,44 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,
> TCGv_i64 arg1, int64_t arg2)
> }
> }
>
> +static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
> + TCGv_i32 arg2, unsigned int ofs,
> + unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i32
> + tcg_gen_op4i_i32(INDEX_op_deposit_i32, ret, arg1, arg2, (ofs << 8) | len);
> +#else
> + uint32_t mask = (1u << len) - 1;
> + TCGv_i32 t1 = tcg_temp_new_i32 ();
> +
> + tcg_gen_andi_i32(t1, arg2, mask);
> + tcg_gen_shli_i32(t1, t1, ofs);
> + tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i32(ret, ret, t1);
> +
> + tcg_temp_free_i32(t1);
> +#endif
> +}
> +
> +static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
> + TCGv_i64 arg2, unsigned int ofs,
> + unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i64
> + tcg_gen_op4i_i64(INDEX_op_deposit_i64, ret, arg1, arg2, (ofs << 8) | len);
> +#else
> + uint64_t mask = (1ull << len) - 1;
> + TCGv_i64 t1 = tcg_temp_new_i64 ();
> +
> + tcg_gen_andi_i64(t1, arg2, mask);
> + tcg_gen_shli_i64(t1, t1, ofs);
> + tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i64(ret, ret, t1);
> +
> + tcg_temp_free_i64(t1);
> +#endif
> +}
> +
> /***************************************/
> /* QEMU specific operations. Their type depend on the QEMU CPU
> type. */
> @@ -2384,6 +2422,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i64
> #define tcg_gen_rotr_tl tcg_gen_rotr_i64
> #define tcg_gen_rotri_tl tcg_gen_rotri_i64
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i64
> #define tcg_const_tl tcg_const_i64
> #define tcg_const_local_tl tcg_const_local_i64
> #else
> @@ -2454,6 +2493,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i32
> #define tcg_gen_rotr_tl tcg_gen_rotr_i32
> #define tcg_gen_rotri_tl tcg_gen_rotri_i32
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i32
> #define tcg_const_tl tcg_const_i32
> #define tcg_const_local_tl tcg_const_local_i32
> #endif
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 2a98fed..ded6311 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -78,6 +78,9 @@ DEF(sar_i32, 1, 2, 0, 0)
> DEF(rotl_i32, 1, 2, 0, 0)
> DEF(rotr_i32, 1, 2, 0, 0)
> #endif
> +#ifdef TCG_TARGET_HAS_deposit_i32
> +DEF(deposit_i32, 1, 2, 1, 0)
> +#endif
>
> DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
> #if TCG_TARGET_REG_BITS == 32
> @@ -168,6 +171,9 @@ DEF(sar_i64, 1, 2, 0, 0)
> DEF(rotl_i64, 1, 2, 0, 0)
> DEF(rotr_i64, 1, 2, 0, 0)
> #endif
> +#ifdef TCG_TARGET_HAS_deposit_i64
> +DEF(deposit_i64, 1, 2, 1, 0)
> +#endif
>
> DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
> #ifdef TCG_TARGET_HAS_ext8s_i64
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 5dd6a2c..e95a42f 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -956,6 +956,19 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
> fprintf(outfile, ",$0x%" TCG_PRIlx, args[k++]);
> i = 1;
> break;
> +#if defined(TCG_TARGET_HAS_deposit_i32) ||
> defined(TCG_TARGET_HAS_deposit_i64)
> +# ifdef TCG_TARGET_HAS_deposit_i32
> + case INDEX_op_deposit_i32:
> +# endif
> +# ifdef TCG_TARGET_HAS_deposit_i64
> + case INDEX_op_deposit_i64:
> +# endif
> + fprintf(outfile, ",%u,%u", (unsigned)args[k] >> 8,
> + (unsigned)args[k] & 0xff);
> + k++;
> + i = 1;
> + break;
> +#endif
Having two constants in the op would avoid this special code.
> default:
> i = 0;
> break;
> --
> 1.7.2.3
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net
