On Mon, Sep 11, 2017 at 07:12:27PM +0200, Cédric Le Goater wrote:
> When an O/S Exception is raised, the O/S acknowledges the interrupt
> with a special read in the TIMA. If the EO bit of the Notification
> Source Register (NSR) is set (and it should), the Current Processor
> Priority Register (CPPR) takes the value of the Pending Interrupt
> Priority Register (PIPR), which contains the priority of the most
> favored pending notification. The bit number corresponding to the
> priority of the pending interrupt is reseted in the Interrupt Pending
> Buffer (IPB) and so is the EO bit of the NSR.
>
> Signed-off-by: Cédric Le Goater <c...@kaod.org>
> ---
> hw/intc/spapr_xive.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index e5d4b723b7e0..ad3ff91b13ea 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -50,7 +50,24 @@ static uint8_t ipb_to_pipr(uint8_t ibp)
>
> static uint64_t spapr_xive_icp_accept(ICPState *icp)
> {
> - return 0;
> + uint8_t nsr = icp->tima_os[TM_NSR];
> +
> + qemu_irq_lower(icp->output);
Ah, here's the lower. This should not be in a different patch from
the matching raise. Plus, this doesn't seem right. Shouldn't this
recheck the CPPR against the PIPR, in case a higher priority irq has
been delivered since the one the cpu is acking.
> + if (icp->tima_os[TM_NSR] & TM_QW1_NSR_EO) {
> + uint8_t cppr = icp->tima_os[TM_PIPR];
> +
> + icp->tima_os[TM_CPPR] = cppr;
> +
> + /* Reset the pending buffer bit */
> + icp->tima_os[TM_IPB] &= ~priority_to_ipb(cppr);
> + icp->tima_os[TM_PIPR] = ipb_to_pipr(icp->tima_os[TM_IPB]);
> +
> + /* Drop Exception bit for OS */
> + icp->tima_os[TM_NSR] &= ~TM_QW1_NSR_EO;
> + }
> +
> + return (nsr << 8) | icp->tima_os[TM_CPPR];
> }
>
> static void spapr_xive_icp_notify(ICPState *icp)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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