On Fri, Nov 19, 2010 at 05:15:19PM +0900, Isaku Yamahata wrote:
> On Thu, Nov 18, 2010 at 10:46:25AM +0200, Michael S. Tsirkin wrote:
> > On Thu, Nov 18, 2010 at 04:29:10PM +0900, Isaku Yamahata wrote:
> > > On Thu, Nov 18, 2010 at 09:05:30AM +0200, Michael S. Tsirkin wrote:
> > > > On Wed, Nov 17, 2010 at 01:50:27PM +0900, Isaku Yamahata wrote:
> > > > > Emulates secondary bus reset when secondary bus reset bit
> > > > > is written from 0 to 1.
> > > > >
> > > > > Signed-off-by: Isaku Yamahata <yamah...@valinux.co.jp>
> > > > > Signed-off-by: Anthony Liguori <aligu...@us.ibm.com>
> > > > > ---
> > > > > hw/pci_bridge.c | 12 +++++++++++-
> > > > > 1 files changed, 11 insertions(+), 1 deletions(-)
> > > > >
> > > > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
> > > > > index 58cc2e4..618a81e 100644
> > > > > --- a/hw/pci_bridge.c
> > > > > +++ b/hw/pci_bridge.c
> > > > > @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice
> > > > > *bridge, uint8_t type)
> > > > > void pci_bridge_write_config(PCIDevice *d,
> > > > > uint32_t address, uint32_t val, int len)
> > > > > {
> > > > > + PCIBridge *s = container_of(d, PCIBridge, dev);
> > > > > + uint16_t bridge_control = pci_get_word(d->config +
> > > > > PCI_BRIDGE_CONTROL);
> > > > > + uint16_t bridge_control_new;
> > > > > +
> > > > > pci_default_write_config(d, address, val, len);
> > > > >
> > > > > if (/* io base/limit */
> > > > > @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d,
> > > > > /* memory base/limit, prefetchable base/limit and
> > > > > io base/limit upper 16 */
> > > > > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
> > > > > - PCIBridge *s = container_of(d, PCIBridge, dev);
> > > > > pci_bridge_update_mappings(&s->sec_bus);
> > > > > }
> > > > > +
> > > > > + bridge_control_new = pci_get_word(d->config +
> > > > > PCI_BRIDGE_CONTROL);
> > > > > + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) &&
> > > > > + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) {
> > > > > + /* 0 -> 1 */
> > > > > + pci_bus_reset(&s->sec_bus);
> > > > > + }
> > > > > }
> > > > >
> > > > > void pci_bridge_disable_base_limit(PCIDevice *dev)
> > > >
> > > > Presumably this bit will have to be made writeable?
> > >
> > > Yes, it's already writable.
> > > static void pci_init_wmask_bridge(PCIDevice *d)
> > > ...
> > > pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
> >
> > Ouch, that's wrong, isn't it?
> > Bits 15:12 are reserved, readonly, 0.
> >
> > I think we need the following (untested).
> > Comments?
>
> Basically it looks good if you left bits 8-11 RO intentional.
> qemu doesn't emulate pci bus cycles, so it won't matter.
>
So this on top?
diff --git a/hw/pci.c b/hw/pci.c
index 7d6d5ad..75da4f7 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -589,7 +589,11 @@ static void pci_init_wmask_bridge(PCIDevice *d)
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
/* TODO: add this define to pci_regs.h in linux and then in qemu. */
-#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
+#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
+#define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard
timer */
+#define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
+#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
+#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_SERR |
@@ -598,7 +602,15 @@ static void pci_init_wmask_bridge(PCIDevice *d)
PCI_BRIDGE_CTL_VGA_16BIT |
PCI_BRIDGE_CTL_MASTER_ABORT |
PCI_BRIDGE_CTL_BUS_RESET |
- PCI_BRIDGE_CTL_FAST_BACK);
+ PCI_BRIDGE_CTL_FAST_BACK |
+ PCI_BRIDGE_CTL_DISCARD |
+ PCI_BRIDGE_CTL_SEC_DISCARD |
+ PCI_BRIDGE_CTL_DISCARD_STATUS |
+ PCI_BRIDGE_CTL_DISCARD_SERR);
+ /* Below does not do anything as we never set this bit, put here for
+ * completeness. */
+ pci_set_word(d->w1mask + PCI_BRIDGE_CONTROL,
+ PCI_BRIDGE_CTL_DISCARD_STATUS);
}
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
