On Thu, Nov 18, 2010 at 10:46:25AM +0200, Michael S. Tsirkin wrote: > On Thu, Nov 18, 2010 at 04:29:10PM +0900, Isaku Yamahata wrote: > > On Thu, Nov 18, 2010 at 09:05:30AM +0200, Michael S. Tsirkin wrote: > > > On Wed, Nov 17, 2010 at 01:50:27PM +0900, Isaku Yamahata wrote: > > > > Emulates secondary bus reset when secondary bus reset bit > > > > is written from 0 to 1. > > > > > > > > Signed-off-by: Isaku Yamahata <yamah...@valinux.co.jp> > > > > Signed-off-by: Anthony Liguori <aligu...@us.ibm.com> > > > > --- > > > > hw/pci_bridge.c | 12 +++++++++++- > > > > 1 files changed, 11 insertions(+), 1 deletions(-) > > > > > > > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c > > > > index 58cc2e4..618a81e 100644 > > > > --- a/hw/pci_bridge.c > > > > +++ b/hw/pci_bridge.c > > > > @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice > > > > *bridge, uint8_t type) > > > > void pci_bridge_write_config(PCIDevice *d, > > > > uint32_t address, uint32_t val, int len) > > > > { > > > > + PCIBridge *s = container_of(d, PCIBridge, dev); > > > > + uint16_t bridge_control = pci_get_word(d->config + > > > > PCI_BRIDGE_CONTROL); > > > > + uint16_t bridge_control_new; > > > > + > > > > pci_default_write_config(d, address, val, len); > > > > > > > > if (/* io base/limit */ > > > > @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, > > > > /* memory base/limit, prefetchable base/limit and > > > > io base/limit upper 16 */ > > > > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { > > > > - PCIBridge *s = container_of(d, PCIBridge, dev); > > > > pci_bridge_update_mappings(&s->sec_bus); > > > > } > > > > + > > > > + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > > > > + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && > > > > + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { > > > > + /* 0 -> 1 */ > > > > + pci_bus_reset(&s->sec_bus); > > > > + } > > > > } > > > > > > > > void pci_bridge_disable_base_limit(PCIDevice *dev) > > > > > > Presumably this bit will have to be made writeable? > > > > Yes, it's already writable. > > static void pci_init_wmask_bridge(PCIDevice *d) > > ... > > pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); > > Ouch, that's wrong, isn't it? > Bits 15:12 are reserved, readonly, 0. > > I think we need the following (untested). > Comments?
Basically it looks good if you left bits 8-11 RO intentional. qemu doesn't emulate pci bus cycles, so it won't matter. Also, please include following hunk. commit 8c76e0427234290a640499c1305cabd998d6f777 Author: Isaku Yamahata <yamah...@valinux.co.jp> Date: Fri Nov 19 17:08:57 2010 +0900 pcie/port: initialize bridge control register properly pci generic layer initialized bridge control register according to pci spec. pcie deviates slightly from it, so initializes it properly. Signed-off-by: Isaku Yamahata <yamah...@valinux.co.jp> diff --git a/hw/pcie_port.c b/hw/pcie_port.c index 117de61..340dcdb 100644 --- a/hw/pcie_port.c +++ b/hw/pcie_port.c @@ -27,6 +27,14 @@ void pcie_port_init_reg(PCIDevice *d) pci_set_word(d->config + PCI_STATUS, 0); pci_set_word(d->config + PCI_SEC_STATUS, 0); + /* Unlike conventional pci bridge, some bits are hardwared to 0. */ + pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, + PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_ISA | + PCI_BRIDGE_CTL_VGA | + PCI_BRIDGE_CTL_SERR | + PCI_BRIDGE_CTL_BUS_RESET); + /* 7.5.3.5 Prefetchable Memory Base Limit * The Prefetchable Memory Base and Prefetchable Memory Limit registers * must indicate that 64-bit addresses are supported, as defined in > > pci: fix bridge control bit wmask > > Bits 12 to 15 in bridge control register are reserver and must be > read-only zero, curent mask is 0xffff which makes them writeable. Fix > this up by using symbolic bit names for writeable bits instead of a > hardcoded constant. > > Signed-off-by: Michael S. Tsirkin <m...@redhat.com> > > -- > > diff --git a/hw/pci.c b/hw/pci.c > index 00ec8ea..7d6d5ad 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -588,7 +588,17 @@ static void pci_init_wmask_bridge(PCIDevice *d) > /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ > memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); > > - pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff); > +/* TODO: add this define to pci_regs.h in linux and then in qemu. */ > +#define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ > + pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, > + PCI_BRIDGE_CTL_PARITY | > + PCI_BRIDGE_CTL_SERR | > + PCI_BRIDGE_CTL_ISA | > + PCI_BRIDGE_CTL_VGA | > + PCI_BRIDGE_CTL_VGA_16BIT | > + PCI_BRIDGE_CTL_MASTER_ABORT | > + PCI_BRIDGE_CTL_BUS_RESET | > + PCI_BRIDGE_CTL_FAST_BACK); > } > > static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) > -- yamahata