Incrementally paves the way towards using the generic instruction translation
loop.
Signed-off-by: Lluís Vilanova <vilan...@ac.upc.edu>
---
target/arm/translate.c | 68 ++++++++++++++++++++++++++++++++----------------
1 file changed, 46 insertions(+), 22 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c7e188b50e..790eaa2164 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11918,6 +11918,32 @@ static void arm_trblock_insn_start(DisasContextBase
*dcbase, CPUState *cpu)
#endif
}
+static BreakpointCheckType arm_trblock_breakpoint_check(
+ DisasContextBase *dcbase, CPUState *cpu, const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ if (bp->flags & BP_CPU) {
+ gen_set_condexec(dc);
+ gen_set_pc_im(dc, dc->pc);
+ gen_helper_check_breakpoints(cpu_env);
+ /* End the TB early; it's likely not going to be executed */
+ dc->base.is_jmp = DISAS_UPDATE;
+ return BC_HIT_INSN;
+ } else {
+ gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
+ /* The address covered by the breakpoint must be
+ included in [tb->pc, tb->pc + tb->size) in order
+ to for it to be properly cleared -- thus we
+ increment the PC here so that the logic setting
+ tb->size below does the right thing. */
+ /* TODO: Advance PC by correct instruction length to
+ * avoid disassembler error messages */
+ dc->pc += 2;
+ return BC_HIT_TB;
+ }
+}
+
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
{
@@ -11965,36 +11991,34 @@ void gen_intermediate_code(CPUState *cpu,
TranslationBlock *tb)
dc->base.num_insns++;
arm_trblock_insn_start(&dc->base, cpu);
- if (unlikely(dc->base.is_jmp > DISAS_NEXT)) {
- break;
- }
-
if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
- if (bp->pc == dc->pc) {
- if (bp->flags & BP_CPU) {
- gen_set_condexec(dc);
- gen_set_pc_im(dc, dc->pc);
- gen_helper_check_breakpoints(cpu_env);
- /* End the TB early; it's likely not going to be
executed */
- dc->base.is_jmp = DISAS_UPDATE;
- } else {
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
- /* The address covered by the breakpoint must be
- included in [tb->pc, tb->pc + tb->size) in order
- to for it to be properly cleared -- thus we
- increment the PC here so that the logic setting
- tb->size below does the right thing. */
- /* TODO: Advance PC by correct instruction length to
- * avoid disassembler error messages */
- dc->pc += 2;
+ if (bp->pc == dc->base.pc_next) {
+ BreakpointCheckType bp_check =
+ arm_trblock_breakpoint_check(&dc->base, cpu, bp);
+ switch (bp_check) {
+ case BC_MISS:
+ /* Target ignored this breakpoint, go to next */
+ break;
+ case BC_HIT_INSN:
+ /* Hit, keep translating */
+ /*
+ * TODO: if we're never going to have more than one
+ * BP in a single address, we can simply use a
+ * bool here.
+ */
+ goto done_breakpoints;
+ case BC_HIT_TB:
+ /* Hit, end TB */
goto done_generating;
+ default:
+ g_assert_not_reached();
}
- break;
}
}
}
+ done_breakpoints:
if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
