I happened to be looking at the GICv3 spec and our implementation, and I realized that we don't correctly calculate the mask values to get group priorities based on BPR values if the NS BPR1 is being used. This BPR, unlike the S BPR1 or the BPR0, has off-by-one semantics, so instead of "use bits [7:1]" being bpr == 0, it is bpr == 1, and so on, with an NS BPR1 value of 0 being impossible.
Patch 3 in this set fixes this error, and fixes the comments so they're actually accurate. Patches 1 and 2 are preliminary bug fixes which ensure that the NS BPR1 values are actually constrained to be greater than 0, so that the assert()s added in patch 3 can't fire. I'm sending this as the last thing before I head out of the door, so will respond to review comments in June... thanks -- PMM Peter Maydell (3): hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1 hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1 hw/intc/arm_gicv3_cpuif.c | 49 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 5 deletions(-) -- 2.7.4
