This series adds sun4v support. Its v2 was previously submitted via Richard's tree, but produced a clang warning due to a missing #ifdef.
v2 -> v3: added an #ifdef to avoid unused function warning in user mode The following changes since commit 23eb9e6b6d5315171cc15969bbc755f258004df0: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-01-16' into staging (2017-01-17 13:53:50 +0000) are available in the git repository at: https://github.com/artyom-tarasenko/qemu/ tags/pull-sun4v-20170118 for you to fetch changes up to a2664ca0eced57dfc9f261fa1b210f24ddac649d: target-sparc: fix up niagara machine (2017-01-18 22:03:44 +0100) ---------------------------------------------------------------- Artyom Tarasenko (30): target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode target-sparc: store cpu super- and hypervisor flags in TB target-sparc: use explicit mmu register pointers target-sparc: add UA2005 TTE bit #defines target-sparc: add UltraSPARC T1 TLB #defines target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE target-sparc: implement UA2005 scratchpad registers target-sparc: implement UltraSPARC-T1 Strand status ASR target-sparc: hypervisor mode takes over nucleus mode target-sparc: implement UA2005 hypervisor traps target-sparc: implement UA2005 GL register target-sparc: implement UA2005 rdhpstate and wrhpstate instructions target-sparc: fix immediate UA2005 traps target-sparc: use direct address translation in hyperprivileged mode target-sparc: allow priveleged ASIs in hyperprivileged mode target-sparc: ignore writes to UA2005 CPU mondo queue register target-sparc: replace the last tlb entry when no free entries left target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs target-sparc: implement UA2005 TSB Pointers target-sparc: simplify ultrasparc_tsb_pointer target-sparc: allow 256M sized pages target-sparc: implement auto-demapping for UA2005 CPUs target-sparc: add more registers to dump_mmu target-sparc: implement UA2005 ASI_MMU (0x21) target-sparc: store the UA2005 entries in sun4u format target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs target-sparc: implement sun4v RTC target-sparc: move common cpu initialisation routines to sparc64.c target-sparc: fix up niagara machine MAINTAINERS | 7 + default-configs/sparc64-softmmu.mak | 2 + hw/sparc64/Makefile.objs | 2 + hw/sparc64/niagara.c | 177 +++++++++++++++++ hw/sparc64/sparc64.c | 378 +++++++++++++++++++++++++++++++++++ hw/sparc64/sun4u.c | 379 +---------------------------------- hw/timer/Makefile.objs | 2 + hw/timer/sun4v-rtc.c | 102 ++++++++++ include/hw/sparc/sparc64.h | 5 + include/hw/timer/sun4v-rtc.h | 1 + linux-user/main.c | 2 +- qemu-doc.texi | 14 +- target/sparc/asi.h | 1 + target/sparc/cpu.c | 13 +- target/sparc/cpu.h | 105 +++++++--- target/sparc/helper.h | 1 + target/sparc/int64_helper.c | 43 +++- target/sparc/ldst_helper.c | 387 ++++++++++++++++++++++++++++-------- target/sparc/machine.c | 4 +- target/sparc/mmu_helper.c | 20 +- target/sparc/translate.c | 64 +++++- target/sparc/win_helper.c | 46 ++++- 22 files changed, 1227 insertions(+), 528 deletions(-) create mode 100644 hw/sparc64/niagara.c create mode 100644 hw/sparc64/sparc64.c create mode 100644 hw/timer/sun4v-rtc.c create mode 100644 include/hw/sparc/sparc64.h create mode 100644 include/hw/timer/sun4v-rtc.h
