From: Richard Henderson <r...@twiddle.net>
We add s->be_data within do_vec_ld/st. Adding it here means that
we have the wrong bits set in SIZE for a big-endian host, leading
to g_assert_not_reached in write_vec_element and read_vec_element.
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-id: 1481085020-2614-3-git-send-email-...@twiddle.net
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/translate-a64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ef7601b..f673d93 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2830,9 +2830,9 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
} else {
/* Load/store one element per register */
if (is_load) {
- do_vec_ld(s, rt, index, tcg_addr, s->be_data + scale);
+ do_vec_ld(s, rt, index, tcg_addr, scale);
} else {
- do_vec_st(s, rt, index, tcg_addr, s->be_data + scale);
+ do_vec_st(s, rt, index, tcg_addr, scale);
}
}
tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
--
2.7.4
