From: Andrew Gacek <andrew.ga...@gmail.com> When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to 0, the receiver timeout counter should be disabled. See page 1801 of "Zynq-7000 AP SoC Technical Reference Manual". This commit adds a such a check before setting the receive timeout interrupt.
Signed-off-by: Andrew Gacek <andrew.ga...@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> --- hw/char/cadence_uart.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index dba1c53..4dcee57 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -138,9 +138,10 @@ static void fifo_trigger_update(void *opaque) { CadenceUARTState *s = opaque; - s->r[R_CISR] |= UART_INTR_TIMEOUT; - - uart_update_status(s); + if (s->r[R_RTOR]) { + s->r[R_CISR] |= UART_INTR_TIMEOUT; + uart_update_status(s); + } } static void uart_rx_reset(CadenceUARTState *s) -- 2.7.4