Signed-off-by: Richard Henderson <r...@twiddle.net>
---
target-m68k/cpu.h | 1 +
target-m68k/helper.c | 183 +++++++++++++++++++++++++++++++++++++++++++++++-
target-m68k/helper.h | 7 ++
target-m68k/translate.c | 142 ++++++++++++++++++++++++++++++++++++-
4 files changed, 330 insertions(+), 3 deletions(-)
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 0b4ed7b..fc1f16f 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -37,6 +37,7 @@
#define OS_DOUBLE 4
#define OS_EXTENDED 5
#define OS_PACKED 6
+#define OS_UNSIZED 7
#define MAX_QREGS 32
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f750d3d..4b0235c 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -22,8 +22,8 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
-
#include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
#define SIGNBIT (1u << 31)
@@ -756,3 +756,184 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t
val, uint32_t acc)
res |= (uint64_t)(val & 0xffff0000) << 16;
env->macc[acc + 1] = res;
}
+
+struct bf_data {
+ uint64_t mask;
+ uint32_t addr;
+ int bofs;
+ int blen;
+ int len;
+};
+
+static inline struct bf_data bf_prep(uint32_t addr, int32_t ofs, uint32_t len)
+{
+ uint64_t mask;
+ int bofs;
+
+ /* Bound length; map 0 to 32. */
+ len = ((len - 1) & 31) + 1;
+ mask = -1ull << (64 - len);
+
+ /* Note that ofs is signed. */
+ addr += ofs / 8;
+ bofs = ofs % 8;
+ if (bofs < 0) {
+ bofs += 8;
+ addr -= 1;
+ }
+
+ return (struct bf_data){
+ .mask = mask,
+ .addr = addr,
+ .bofs = bofs,
+ .blen = (bofs + len - 1) / 8,
+ .len = len,
+ };
+}
+
+static inline uint64_t bf_load(CPUM68KState *env, struct bf_data *d,
+ uintptr_t ra)
+{
+ uint32_t addr = d->addr;
+ uint64_t data;
+
+ /* Be careful not to read bytes across page boundaries unless
+ absolutely necessary. */
+ switch (d->blen) {
+ case 0:
+ d->bofs += 56;
+ data = cpu_ldub_data_ra(env, addr, ra);
+ break;
+
+ case 1:
+ d->bofs += 16;
+ data = cpu_lduw_data_ra(env, addr, ra);
+ break;
+
+ case 2:
+ if ((addr & 3) <= 1) {
+ d->bofs += (addr & 3) * 8;
+ addr -= (addr & 3);
+ d->addr = addr;
+ }
+ /* fallthru */
+
+ case 3:
+ data = cpu_ldl_data_ra(env, addr, ra);
+ break;
+
+ case 4:
+ if ((addr & 7) <= 3) {
+ d->bofs += (addr & 7) * 8;
+ addr -= (addr & 7);
+ d->addr = addr;
+ }
+ data = cpu_ldq_data_ra(env, addr, ra);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ return data;
+}
+
+static inline void bf_store(CPUM68KState *env, struct bf_data *d,
+ uint64_t data, uintptr_t ra)
+{
+ uint32_t addr = d->addr;
+
+ switch (d->blen) {
+ case 0:
+ cpu_stb_data_ra(env, addr, data, ra);
+ break;
+ case 1:
+ cpu_stw_data_ra(env, addr, data, ra);
+ break;
+ case 2:
+ case 3:
+ cpu_stl_data_ra(env, addr, data, ra);
+ break;
+ case 4:
+ cpu_stq_data_ra(env, addr, data, ra);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+uint32_t HELPER(bfexts_mem)(CPUM68KState *env, uint32_t addr,
+ int32_t ofs, uint32_t len)
+{
+ uintptr_t ra = GETPC();
+ struct bf_data d = bf_prep(addr, ofs, len);
+ uint64_t data = bf_load(env, &d, ra);
+
+ return (int64_t)(data << d.bofs) >> (64 - len);
+}
+
+uint64_t HELPER(bfextu_mem)(CPUM68KState *env, uint32_t addr,
+ int32_t ofs, uint32_t len)
+{
+ uintptr_t ra = GETPC();
+ struct bf_data d = bf_prep(addr, ofs, len);
+ uint64_t data = bf_load(env, &d, ra);
+
+ /* Put CC_N at the top of the high word; put the zero-extended value
+ at the bottom of the low word. */
+ data <<= d.bofs;
+ data &= d.mask;
+ data |= data >> (64 - d.len);
+ return data;
+}
+
+uint32_t HELPER(bfins_mem)(CPUM68KState *env, uint32_t addr, uint32_t val,
+ int32_t ofs, uint32_t len)
+{
+ uintptr_t ra = GETPC();
+ struct bf_data d = bf_prep(addr, ofs, len);
+ uint64_t data = bf_load(env, &d, ra);
+
+ data = (data & ~(d.mask >> d.bofs)) | (((uint64_t)val << 32) >> d.bofs);
+
+ bf_store(env, &d, data, ra);
+
+ /* The field at the top of the word is also CC_N for CC_OP_LOGIC. */
+ return val;
+}
+
+uint32_t HELPER(bfchg_mem)(CPUM68KState *env, uint32_t addr,
+ int32_t ofs, uint32_t len)
+{
+ uintptr_t ra = GETPC();
+ struct bf_data d = bf_prep(addr, ofs, len);
+ uint64_t data = bf_load(env, &d, ra);
+
+ bf_store(env, &d, data ^ (d.mask >> d.bofs), ra);
+
+ return (data << d.bofs) >> 32;
+}
+
+uint32_t HELPER(bfclr_mem)(CPUM68KState *env, uint32_t addr,
+ int32_t ofs, uint32_t len)
+{
+ uintptr_t ra = GETPC();
+ struct bf_data d = bf_prep(addr, ofs, len);
+ uint64_t data = bf_load(env, &d, ra);
+
+ bf_store(env, &d, data &~ (d.mask >> d.bofs), ra);
+
+ return (data << d.bofs) >> 32;
+}
+
+uint32_t HELPER(bfset_mem)(CPUM68KState *env, uint32_t addr,
+ int32_t ofs, uint32_t len)
+{
+ uintptr_t ra = GETPC();
+ struct bf_data d = bf_prep(addr, ofs, len);
+ uint64_t data = bf_load(env, &d, ra);
+
+ bf_store(env, &d, data | (d.mask >> d.bofs), ra);
+
+ return (data << d.bofs) >> 32;
+}
diff --git a/target-m68k/helper.h b/target-m68k/helper.h
index d863e55..8db741a 100644
--- a/target-m68k/helper.h
+++ b/target-m68k/helper.h
@@ -48,3 +48,10 @@ DEF_HELPER_2(flush_flags, void, env, i32)
DEF_HELPER_2(set_ccr, void, env, i32)
DEF_HELPER_FLAGS_1(get_ccr, TCG_CALL_NO_WG_SE, i32, env)
DEF_HELPER_2(raise_exception, void, env, i32)
+
+DEF_HELPER_FLAGS_4(bfexts_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
+DEF_HELPER_FLAGS_4(bfextu_mem, TCG_CALL_NO_WG, i64, env, i32, s32, i32)
+DEF_HELPER_FLAGS_5(bfins_mem, TCG_CALL_NO_WG, i32, env, i32, i32, s32, i32)
+DEF_HELPER_FLAGS_4(bfchg_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
+DEF_HELPER_FLAGS_4(bfclr_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
+DEF_HELPER_FLAGS_4(bfset_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 477a511..d2dd4bd 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -709,10 +709,17 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext
*s,
case 0: /* Data register direct. */
case 1: /* Address register direct. */
return NULL_QREG;
- case 2: /* Indirect register */
case 3: /* Indirect postincrement. */
+ if (opsize == OS_UNSIZED) {
+ return NULL_QREG;
+ }
+ /* fallthru */
+ case 2: /* Indirect register */
return get_areg(s, reg0);
case 4: /* Indirect predecrememnt. */
+ if (opsize == OS_UNSIZED) {
+ return NULL_QREG;
+ }
reg = get_areg(s, reg0);
tmp = tcg_temp_new();
tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
@@ -2786,6 +2793,49 @@ DISAS_INSN(bfext_reg)
set_cc_op(s, CC_OP_LOGIC);
}
+DISAS_INSN(bfext_mem)
+{
+ int ext = read_im16(env, s);
+ int is_sign = insn & 0x200;
+ TCGv dest = DREG(ext, 12);
+ TCGv addr, len, ofs;
+
+ addr = gen_lea(env, s, insn, OS_UNSIZED);
+ if (IS_NULL_QREG(addr)) {
+ gen_addr_fault(s);
+ return;
+ }
+
+ if (ext & 0x20) {
+ len = DREG(ext, 0);
+ } else {
+ len = tcg_const_i32(extract32(ext, 0, 5));
+ }
+ if (ext & 0x800) {
+ ofs = DREG(ext, 6);
+ } else {
+ ofs = tcg_const_i32(extract32(ext, 6, 5));
+ }
+
+ if (is_sign) {
+ gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
+ tcg_gen_mov_i32(QREG_CC_N, dest);
+ } else {
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
+ tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
+ tcg_temp_free_i64(tmp);
+ }
+ set_cc_op(s, CC_OP_LOGIC);
+
+ if (!(ext & 0x20)) {
+ tcg_temp_free(len);
+ }
+ if (!(ext & 0x800)) {
+ tcg_temp_free(ofs);
+ }
+}
+
DISAS_INSN(bfop_reg)
{
int ext = read_im16(env, s);
@@ -2851,6 +2901,54 @@ DISAS_INSN(bfop_reg)
tcg_temp_free(mask);
}
+DISAS_INSN(bfop_mem)
+{
+ int ext = read_im16(env, s);
+ TCGv addr, len, ofs;
+
+ addr = gen_lea(env, s, insn, OS_UNSIZED);
+ if (IS_NULL_QREG(addr)) {
+ gen_addr_fault(s);
+ return;
+ }
+
+ if (ext & 0x20) {
+ len = DREG(ext, 0);
+ } else {
+ len = tcg_const_i32(extract32(ext, 0, 5));
+ }
+ if (ext & 0x800) {
+ ofs = DREG(ext, 6);
+ } else {
+ ofs = tcg_const_i32(extract32(ext, 6, 5));
+ }
+
+ switch (insn & 0x0f00) {
+ case 0x0a00: /* bfchg */
+ gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ break;
+ case 0x0c00: /* bfclr */
+ gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ break;
+ case 0x0e00: /* bfset */
+ gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ break;
+ case 0x0800: /* bftst */
+ gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ set_cc_op(s, CC_OP_LOGIC);
+
+ if (!(ext & 0x20)) {
+ tcg_temp_free(len);
+ }
+ if (!(ext & 0x800)) {
+ tcg_temp_free(ofs);
+ }
+}
+
DISAS_INSN(bfins_reg)
{
int ext = read_im16(env, s);
@@ -2925,6 +3023,40 @@ DISAS_INSN(bfins_reg)
tcg_temp_free(tmp);
}
+DISAS_INSN(bfins_mem)
+{
+ int ext = read_im16(env, s);
+ TCGv src = DREG(ext, 12);
+ TCGv addr, len, ofs;
+
+ addr = gen_lea(env, s, insn, OS_UNSIZED);
+ if (IS_NULL_QREG(addr)) {
+ gen_addr_fault(s);
+ return;
+ }
+
+ if (ext & 0x20) {
+ len = DREG(ext, 0);
+ } else {
+ len = tcg_const_i32(extract32(ext, 0, 5));
+ }
+ if (ext & 0x800) {
+ ofs = DREG(ext, 6);
+ } else {
+ ofs = tcg_const_i32(extract32(ext, 6, 5));
+ }
+
+ gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
+ set_cc_op(s, CC_OP_LOGIC);
+
+ if (!(ext & 0x20)) {
+ tcg_temp_free(len);
+ }
+ if (!(ext & 0x800)) {
+ tcg_temp_free(ofs);
+ }
+}
+
DISAS_INSN(ff1)
{
TCGv reg;
@@ -3999,11 +4131,17 @@ void register_m68k_insns (CPUM68KState *env)
INSN(shift16_reg, e060, f0f0, M68000);
INSN(shift_reg, e0a0, f0f0, M68000);
INSN(shift_mem, e0c0, fcc0, M68000);
- INSN(bfext_reg, e9c0, fdf8, BITFIELD); /* bfextu & bfexts */
+ INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
+ INSN(bfext_reg, e9c0, fdf8, BITFIELD);
+ INSN(bfins_mem, efc0, ffc0, BITFIELD);
INSN(bfins_reg, efc0, fff8, BITFIELD);
+ INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
+ INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
+ INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
+ INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
INSN(undef_fpu, f000, f000, CF_ISA_A);
INSN(fpu, f200, ffc0, CF_FPU);
--
2.7.4
