This is v7, with the additional fix for gcc 4.2, as on Centos 6.
r~
The following changes since commit da158a86c407fa7b9da848b571356a26809d8df9:
Merge remote-tracking branch
'remotes/berrange/tags/pull-qcrypto-2016-10-20-1' into staging (2016-10-20
14:46:19 +0100)
are available in the git repository at:
git://github.com/rth7680/qemu.git tags/pull-atomic-20161022
for you to fetch changes up to 278c5beb29ef8b6747a7c9bde403e9fe90cdad9c:
target-alpha: Emulate LL/SC using cmpxchg helpers (2016-10-20 11:00:46 -0700)
----------------------------------------------------------------
cmpxchg atomic operations
----------------------------------------------------------------
Alex Bennée (1):
linux-user: enable parallel code generation on clone
Emilio G. Cota (18):
atomics: add atomic_xor
atomics: add atomic_op_fetch variants
target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers
target-i386: emulate LOCK'ed OP instructions using atomic helpers
target-i386: emulate LOCK'ed INC using atomic helper
target-i386: emulate LOCK'ed NOT using atomic helper
target-i386: emulate LOCK'ed NEG using cmpxchg helper
target-i386: emulate LOCK'ed XADD using atomic helper
target-i386: emulate LOCK'ed BTX ops using atomic helpers
target-i386: emulate XCHG using atomic helper
target-i386: remove helper_lock()
tests: add atomic_add-bench
target-arm: emulate LL/SC using cmpxchg helpers
target-arm: emulate SWP with atomic_xchg helper
target-arm: emulate aarch64's LL/SC using cmpxchg helpers
linux-user: remove handling of ARM's EXCP_STREX
linux-user: remove handling of aarch64's EXCP_STREX
target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}
Richard Henderson (16):
exec: Avoid direct references to Int128 parts
int128: Use __int128 if available
int128: Add int128_make128
tcg: Add EXCP_ATOMIC
cputlb: Replace SHIFT with DATA_SIZE
cputlb: Move probe_write out of softmmu_template.h
cputlb: Remove includes from softmmu_template.h
cputlb: Move most of iotlb code out of line
cputlb: Tidy some macros
tcg: Add atomic helpers
tcg: Add atomic128 helpers
tcg: Add CONFIG_ATOMIC64
tcg: Emit barriers with parallel_cpus
target-arm: Rearrange aa32 load and store functions
target-alpha: Introduce MMU_PHYS_IDX
target-alpha: Emulate LL/SC using cmpxchg helpers
Makefile.objs | 2 +-
Makefile.target | 1 +
atomic_template.h | 215 +++++++++++++++++++++++++
configure | 62 +++++++-
cpu-exec-common.c | 6 +
cpu-exec.c | 30 ++++
cpus.c | 2 +
cputlb.c | 203 ++++++++++++++++++++++--
exec.c | 4 +-
include/exec/cpu-all.h | 1 +
include/exec/exec-all.h | 1 +
include/qemu-common.h | 1 +
include/qemu/atomic.h | 67 ++++++--
include/qemu/int128.h | 171 +++++++++++++++++++-
linux-user/main.c | 312 ++++++------------------------------
linux-user/syscall.c | 8 +
softmmu_template.h | 104 ++----------
target-alpha/cpu.h | 22 +--
target-alpha/helper.c | 14 +-
target-alpha/helper.h | 9 --
target-alpha/machine.c | 2 -
target-alpha/mem_helper.c | 73 ---------
target-alpha/translate.c | 148 +++++++++--------
target-arm/cpu.h | 17 +-
target-arm/helper-a64.c | 113 +++++++++++++
target-arm/helper-a64.h | 2 +
target-arm/internals.h | 4 +-
target-arm/translate-a64.c | 106 ++++++-------
target-arm/translate.c | 344 +++++++++++++++-------------------------
target-arm/translate.h | 4 -
target-i386/helper.h | 4 +-
target-i386/mem_helper.c | 153 ++++++++++++------
target-i386/translate.c | 386 +++++++++++++++++++++++++++++----------------
tcg-runtime.c | 74 +++++++--
tcg/tcg-op.c | 354 +++++++++++++++++++++++++++++++++++++++--
tcg/tcg-op.h | 44 ++++++
tcg/tcg-runtime.h | 109 +++++++++++++
tcg/tcg.h | 85 ++++++++++
tests/.gitignore | 1 +
tests/Makefile.include | 4 +-
tests/atomic_add-bench.c | 163 +++++++++++++++++++
tests/test-int128.c | 22 +--
translate-all.c | 1 +
43 files changed, 2353 insertions(+), 1095 deletions(-)
create mode 100644 atomic_template.h
create mode 100644 tests/atomic_add-bench.c
